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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_DVBC_INTERN.h 98 /// @brief DVBC Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_DVBC_V2_H_ 103 #define _DRV_DVBC_V2_H_ 104 105 //#include "MsCommon.h" 106 //#include "drvDMD_common.h" 107 #include "drvDMD_INTERN_DVBC.h" 108 #ifdef __cplusplus 109 extern "C" 110 { 111 #endif 112 113 #ifndef DLL_PUBLIC 114 #define DLL_PUBLIC 115 #endif 116 117 118 #define DMD_DVBC_MAX_DEMOD_NUM 1 119 120 121 122 //------------------------------------------------------------------------------------------------- 123 // Driver Capability 124 //------------------------------------------------------------------------------------------------- 125 typedef struct DLL_PACKED 126 { 127 MS_BOOL b_DCOFF_IsDVBC; 128 MS_BOOL b_IsInit_DVBCCreat; 129 EN_POWER_MODE eLastState; 130 } DMD_DVBC_SHARE_MEMORY_InitData; 131 132 typedef struct DLL_PACKED 133 { 134 MS_U16 u16Version; 135 MS_U16 u16SymbolRate; 136 DMD_DVBC_MODULATION_TYPE eQamMode; 137 MS_U32 u32IFFreq; 138 MS_BOOL bSpecInv; 139 MS_BOOL bSerialTS; 140 MS_U8 u8SarValue; 141 MS_U32 u32ChkScanTimeStart; 142 DMD_DVBC_LOCK_STATUS eLockStatus; 143 MS_U16 u16Strength; 144 MS_U16 u16Quality; 145 MS_U32 u32Intp; 146 MS_U32 u32FcFs; 147 MS_U8 u8Qam; 148 MS_U16 u16SymbolRateHal; 149 } DMD_DVBC_SHARE_MEMORY_PreviousData; 150 151 typedef struct DLL_PACKED 152 { 153 // tuner parameter 154 MS_U8 u8SarChannel; 155 156 /* 157 DMD_RFAGC_SSI *pTuner_RfagcSsi; 158 MS_U16 u16Tuner_RfagcSsi_Size; 159 DMD_IFAGC_SSI *pTuner_IfagcSsi_LoRef; 160 MS_U16 u16Tuner_IfagcSsi_LoRef_Size; 161 DMD_IFAGC_SSI *pTuner_IfagcSsi_HiRef; 162 MS_U16 u16Tuner_IfagcSsi_HiRef_Size; 163 DMD_IFAGC_ERR *pTuner_IfagcErr_LoRef; 164 MS_U16 u16Tuner_IfagcErr_LoRef_Size; 165 DMD_IFAGC_ERR *pTuner_IfagcErr_HiRef; 166 MS_U16 u16Tuner_IfagcErr_HiRef_Size; 167 DMD_SQI_CN_NORDIGP1 *pSqiCnNordigP1; 168 MS_U16 u16SqiCnNordigP1_Size; 169 */ 170 // register init 171 MS_U8 *u8DMD_DVBC_DSPRegInitExt; // TODO use system variable type 172 MS_U8 u8DMD_DVBC_DSPRegInitSize; 173 MS_U8 *u8DMD_DVBC_InitExt; // TODO use system variable type 174 } DMD_DVBC_InitData_Transform; 175 176 typedef struct DLL_PACKED 177 { 178 DMD_DVBC_SHARE_MEMORY_InitData sDMD_DVBC_SHARE_MEMORY_InitData; 179 DMD_DVBC_SHARE_MEMORY_PreviousData sDMD_DVBC_SHARE_MEMORY_PreviousData; 180 DMD_DVBC_InitData_Transform sDMD_DVBC_InitData_Transform; 181 } DMD_DVBC_ResData; 182 183 184 185 186 187 188 typedef enum { 189 DMD_DVBC_DRV_CMD_Dual_Public_Init, 190 DMD_DVBC_DRV_CMD_Dual_Individual_Init, 191 DMD_DVBC_DRV_CMD_Init, 192 DMD_DVBC_DRV_CMD_Exit, 193 DMD_DVBC_DRV_CMD_SetDbgLevel, 194 DMD_DVBC_DRV_CMD_GetInfo, 195 DMD_DVBC_DRV_CMD_GetLibVer, 196 DMD_DVBC_DRV_CMD_GetFWVer, 197 DMD_DVBC_DRV_CMD_GetDSPReg, 198 DMD_DVBC_DRV_CMD_SetDSPReg, 199 DMD_DVBC_DRV_CMD_GetReg, 200 DMD_DVBC_DRV_CMD_SetReg, 201 DMD_DVBC_DRV_CMD_SetSerialControl, 202 DMD_DVBC_DRV_CMD_SetConfig, 203 DMD_DVBC_DRV_CMD_SetSetConfig_symbol_rate_list, 204 DMD_DVBC_DRV_CMD_SetActive, 205 DMD_DVBC_DRV_CMD_GetLockWithRFPower, 206 DMD_DVBC_DRV_CMD_GetSignalStrengthWithRFPower, 207 DMD_DVBC_DRV_CMD_GetSignalQualityWithRFPower, 208 DMD_DVBC_DRV_CMD_ActiveDmdSwitch, 209 DMD_DVBC_DRV_CMD_GetSNR, 210 DMD_DVBC_DRV_CMD_GetPostViterbiBer, 211 DMD_DVBC_DRV_CMD_GetPacketErr, 212 DMD_DVBC_DRV_CMD_GetCellID, 213 DMD_DVBC_DRV_CMD_GetStatus, 214 DMD_DVBC_DRV_CMD_SetPowerState, 215 216 //waiting add 217 DMD_DVBC_DRV_CMD_GetIFAGC, 218 219 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO 220 DMD_DVBC_DRV_CMD_GetAGCInfo, 221 #endif 222 } DMD_DVBC_DRV_COMMAND; 223 224 225 226 227 228 typedef struct DLL_PACKED _DVBC_Dual_Public_Init_PARAM 229 { 230 MS_U8 u8AGC_Tristate_Ctrl; 231 MS_U8 u8Sar_Channel; 232 MS_BOOL ret; 233 } DVBC_Dual_Public_Init_PARAM,*PDVBC_Dual_Public_Init_PARAM; 234 235 typedef struct DLL_PACKED _DVBC_Dual_Individual_Init_PARAM 236 { 237 DMD_DVBC_InitData_Transform *pDMD_DVBC_InitData; 238 MS_U32 u32InitDataLen; 239 MS_BOOL ret; 240 }DVBC_Dual_Individual_Init_PARAM,*PDVBC_Dual_Individual_Init_PARAM; 241 242 typedef struct DLL_PACKED _DVBC_Init_PARAM 243 { 244 DMD_DVBC_InitData_Transform *pDMD_DVBC_InitData; 245 MS_U32 u32InitDataLen; 246 MS_BOOL ret; 247 }DVBC_Init_PARAM,*PDVBC_Init_PARAM; 248 249 typedef struct DLL_PACKED _DVBC_SetDbgLevel_PARAM 250 { 251 DMD_DVBC_DbgLv u8DbgLevel; 252 MS_BOOL ret; 253 }DVBC_SetDbgLevel_PARAM,*PDVBC_SetDbgLevel_PARAM; 254 255 typedef struct DLL_PACKED _DVBC_EXIT_PARAM_PARAM 256 { 257 MS_BOOL ret; 258 }DVBC_EXIT_PARAM_PARAM,*PDVBC_EXIT_PARAM_PARAM; 259 260 typedef struct DLL_PACKED _DVBC_GetInfo_PARAM 261 { 262 const DMD_DVBC_Info* ret_info; 263 }DVBC_GetInfo_PARAM,*PDVBC_GetInfo_PARAM; 264 265 typedef struct _DVBC_GetLibVer_PARAM 266 { 267 const MSIF_Version **ppVersion; 268 MS_BOOL ret; 269 }DVBC_GetLibVer_PARAM,*PDVBC_GetLibVer_PARAM; 270 271 typedef struct DLL_PACKED _DVBC_GetFWVer_PARAM 272 { 273 MS_U16 *ver; 274 MS_BOOL ret; 275 }DVBC_GetFWVer_PARAM,*PDVBC_GetFWVer_PARAM; 276 277 278 typedef struct DLL_PACKED _DVBC_GetDSPReg_PARAM 279 { 280 MS_U16 u16Addr; 281 MS_U8 *pu8Data; 282 MS_BOOL ret; 283 }DVBC_GetDSPReg_PARAM,*PDVBC_GetDSPReg_PARAM; 284 285 typedef struct DLL_PACKED _DVBC_SetDSPReg_PARAM 286 { 287 MS_U16 u16Addr; 288 MS_U8 pu8Data; 289 MS_BOOL ret; 290 }DVBC_SetDSPReg_PARAM,*PDVBC_SetDSPReg_PARAM; 291 292 293 typedef struct DLL_PACKED _DVBC_GetReg_PARAM 294 { 295 MS_U16 u16Addr; 296 MS_U8 *pu8Data; 297 MS_BOOL ret; 298 }DVBC_GetReg_PARAM,*PDVBC_GetReg_PARAM; 299 300 typedef struct DLL_PACKED _DVBC_SetReg_PARAM 301 { 302 MS_U16 u16Addr; 303 MS_U8 u8Data; 304 MS_BOOL ret; 305 }DVBC_SetReg_PARAM,*PDVBC_SetReg_PARAM; 306 307 308 typedef struct DLL_PACKED _DVBC_SetSerialControl_PARAM 309 { 310 MS_BOOL bEnable; 311 MS_BOOL ret; 312 }DVBC_SetSerialControl_PARAM,*PDVBC_SetSerialControl_PARAM; 313 314 315 typedef struct DLL_PACKED _DVBC_SetConfig_Symbol_rate_list_PARAM 316 { 317 MS_U16 u16SymbolRate; 318 DMD_DVBC_MODULATION_TYPE eQamMode; 319 MS_U32 u32IFFreq; 320 MS_BOOL bSpecInv; 321 MS_BOOL bSerialTS; 322 MS_U16 *pu16_symbol_rate_list; 323 MS_U8 u8_symbol_rate_list_num; 324 MS_BOOL ret; 325 }DVBC_SetConfig_Symbol_rate_list_PARAM,*PDVBC_SetConfig_Symbol_rate_list_PARAM; 326 327 typedef struct DLL_PACKED _DVBC_SetActive_PARAM 328 { 329 MS_BOOL bEnable; 330 MS_BOOL ret; 331 }DVBC_SetActive_PARAM,*PDVBC_SetActive_PARAM; 332 333 /* 334 typedef struct DLL_PACKED _DVBC_GetLockWithRFPower_Transform 335 { 336 DMD_DVBC_GETLOCK_TYPE eType; 337 DMD_DVBC_LOCK_STATUS *eLockStatus; 338 MS_BOOL ret; 339 }DVBC_GetLockWithRFPower_Transform,*PDVBC_GetLockWithRFPower_Transform; 340 */ 341 342 typedef struct DLL_PACKED _DVBC_GetLockWithRFPower 343 { 344 DMD_DVBC_GETLOCK_TYPE eType; 345 MS_U32 u32CurrRFPowerDbm; 346 MS_U32 u32NoChannelRFPowerDbm; 347 MS_U32 u32TimeInterval; 348 DMD_DVBC_LOCK_STATUS *eLockStatus; 349 MS_BOOL ret; 350 }DVBC_GetLockWithRFPower,*PDVBC_GetLockWithRFPower; 351 352 /* 353 typedef struct _DVBC_GetSignalStrengthWithRFPower_PARAM 354 { 355 MS_U16 *u16Strength; 356 MS_BOOL ret; 357 }DVBC_GetSignalStrengthWithRFPower_PARAM,*PDVBC_GetSignalStrengthWithRFPower_PARAM; 358 359 360 typedef struct _DVBC_GetSignalQualityWithRFPower_PARAM 361 { 362 MS_U16 *u16Quality; 363 MS_BOOL ret; 364 }DVBC_GetSignalQualityWithRFPower_PARAM,*PDVBC_GetSignalQualityWithRFPower_PARAM; 365 */ 366 367 typedef struct DLL_PACKED _DVBC_ActiveDmdSwitch_PARAM 368 { 369 MS_U8 demod_no; 370 MS_BOOL ret; 371 }DVBC_ActiveDmdSwitch_PARAM,*PDVBC_ActiveDmdSwitch_PARAM; 372 373 //waiting add 374 typedef struct _DVBC_GetIFAGC_PARAM 375 { 376 MS_U8 *ifagc_reg; 377 MS_U8 *ifagc_reg_lsb; 378 MS_U16 *ifagc_err_reg; 379 MS_BOOL ret; 380 }DVBC_GetIFAGC_PARAM,*PDVBC_GetIFAGC_PARAM; 381 382 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO 383 typedef struct _DVBC_GetAGCInfo_PARAM 384 { 385 MS_U8 u8dbg_mode; 386 MS_U16 *pu16Data; 387 MS_BOOL ret; 388 }DVBC_GetAGCInfo_PARAM,*PDVBC_GetAGCInfo_PARAM; 389 #endif 390 391 392 //typedef struct DLL_PACKED _DVBC_GetPacketErr_PARAM 393 394 typedef struct _DVBC_GetSNR_PARAM 395 { 396 MS_U16 *snr_reg; 397 MS_BOOL ret; 398 }DVBC_GetSNR_PARAM,*PDVBC_GetSNR_PARAM; 399 400 401 typedef struct _DVBC_GetPostViterbiBer_PARAM 402 { 403 MS_U32 *BitErr_reg; 404 MS_U16 *BitErrPeriod_reg; 405 MS_BOOL ret; 406 }DVBC_GetPostViterbiBer_PARAM,*PDVBC_GetPostViterbiBer_PARAM; 407 408 409 typedef struct DLL_PACKED _DVBC_GetPacketErr_PARAM 410 { 411 MS_U16 *pktErr; 412 MS_BOOL ret; 413 }DVBC_GetPacketErr_PARAM,*PDVBC_GetPacketErr_PARAM; 414 415 typedef struct DLL_PACKED _DVBC_GetCellID_PARAM 416 { 417 MS_U16 *u16CellID; 418 MS_BOOL ret; 419 }DVBC_GetCellID_PARAM,*PDVBC_GetCellID_PARAM; 420 421 422 typedef struct _DVBC_GetStatus_PARAM 423 { 424 DMD_DVBC_MODULATION_TYPE *pQAMMode; 425 MS_U16 *u16SymbolRate; 426 MS_U32 *config_Fc_reg; 427 MS_U32 *Fc_over_Fs_reg; 428 MS_U16 *Cfo_offset_reg; 429 MS_BOOL ret; 430 }DVBC_GetStatus_PARAM,*PDVBC_GetStatus_PARAM; 431 432 433 typedef struct DLL_PACKED _DVBC_SetPowerState_PARAM 434 { 435 EN_POWER_MODE u16PowerState; 436 MS_U32 ret_U32; 437 }DVBC_SetPowerState_PARAM,*PDVBC_SetPowerState_PARAM; 438 439 void DVBCRegisterToUtopia(void); 440 441 442 443 444 /*******kernel mode transform structure***************/ 445 446 447 448 449 450 /*************************************************/ 451 452 453 MS_U32 DVBCOpen(void** pInstantTmp, MS_U32 u32ModuleVersion, void* pAttribute); 454 MS_U32 DVBCClose(void* pInstantTmp); 455 MS_U32 DVBCIoctl(void* pInstantTmp, MS_U32 u32Cmd, void* pArgs); 456 //MS_U32 DVBCStr(MS_U32 u32PowerState, void* pModule); 457 458 459 #ifdef __cplusplus 460 } 461 #endif 462 463 #endif // _DRV_DVBC_H_ 464 465