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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 ////////////////////////////////////////////////////////////////////////////////////////////////// 78 // 79 // @file mdrv_xc_st.h 80 // @brief XC KMD Driver Interface 81 // @author MStar Semiconductor Inc. 82 ////////////////////////////////////////////////////////////////////////////////////////////////// 83 84 85 #ifndef _MDRV_XC_ST_H 86 #define _MDRV_XC_ST_H 87 88 //============================================================================= 89 // Includs 90 //============================================================================= 91 92 //============================================================================= 93 // Type and Structure Declaration 94 //============================================================================= 95 #define KDRV_XC_HDMI_HDR_METADATA_VERSION 0 96 #define KDRV_XC_PANEL_FORMAT_VERSION 0 97 #define KDRV_XC_OSD_CONTROL_VERSION 0 98 #define KDRV_XC_MAIN_CONTROL_VERSION 0 99 #define KDRV_XC_HDMI_INFOFRAME_PARSER_VERSION 0 100 #define KDRV_XC_HDMI_EDID_PARSER_VERSION 0 101 #define KDRV_XC_MM_PARSER_VERSION 0 102 103 typedef struct 104 { 105 MS_BOOL bCurveChange; // Curve Change 106 MS_U8 u8LumaCurve[16]; // Default luma curve from Supernova DLC.ini 107 MS_U8 u8LumaCurve2_a[16]; // Default luma curve 2a from Supernova DLC.ini 108 MS_U8 u8LumaCurve2_b[16]; // Default luma curve 2b from Supernova DLC.ini 109 MS_U8 u8Result; //Out 110 } ST_KDRV_XC_DLC_INFO; 111 112 typedef struct 113 { 114 MS_BOOL bBLEPointChange; // BLE Point Change 115 MS_U16 u16BLESlopPoint[6]; // Default BLE Slop Point from Supernova DLC.ini 116 MS_U8 u8Result; //Out 117 } ST_KDRV_XC_DLC_BLE_INFO; 118 119 typedef struct 120 { 121 MS_BOOL bInitInfoChange; // Init Info Change 122 123 // Default luma curve 124 MS_U8 au8LumaCurve[16]; 125 MS_U8 au8LumaCurve2_a[16]; 126 MS_U8 au8LumaCurve2_b[16]; 127 MS_U8 au8DlcHistogramLimitCurve[17]; 128 129 MS_U8 u8DlcPureImageMode; // Compare difference of max and min bright 130 MS_U8 u8DlcLevelLimit; // n = 0 ~ 4 => Limit n levels => ex. n=2, limit 2 level 0xF7, 0xE7 131 MS_U8 u8DlcAvgDelta; // n = 0 ~ 50, default value: 12 132 MS_U8 u8DlcAvgDeltaStill; // n = 0 ~ 15 => 0: disable still curve, 1 ~ 15 => 0.1 ~ 1.5 enable still curve 133 MS_U8 u8DlcFastAlphaBlending; // min 17 ~ max 32 134 MS_U8 u8DlcYAvgThresholdL; // default value: 0 135 MS_U8 u8DlcYAvgThresholdH; // default value: 128 136 137 MS_U8 u8DlcBLEPoint; // n = 24 ~ 64, default value: 48 138 MS_U8 u8DlcWLEPoint; // n = 24 ~ 64, default value: 48 139 MS_U8 bEnableBLE : 1; // 1: enable; 0: disable 140 MS_U8 bEnableWLE : 1; // 1: enable; 0: disable 141 MS_U8 u8DlcYAvgThresholdM; 142 MS_U8 u8DlcCurveMode; 143 MS_U8 u8DlcCurveModeMixAlpha; 144 MS_U8 u8DlcAlgorithmMode; 145 MS_U8 u8DlcSepPointH; 146 MS_U8 u8DlcSepPointL; 147 MS_U16 u16DlcBleStartPointTH; 148 MS_U16 u16DlcBleEndPointTH; 149 MS_U8 u8DlcCurveDiff_L_TH; 150 MS_U8 u8DlcCurveDiff_H_TH; 151 MS_U16 u16DlcBLESlopPoint_1; 152 MS_U16 u16DlcBLESlopPoint_2; 153 MS_U16 u16DlcBLESlopPoint_3; 154 MS_U16 u16DlcBLESlopPoint_4; 155 MS_U16 u16DlcBLESlopPoint_5; 156 MS_U16 u16DlcDark_BLE_Slop_Min; 157 MS_U8 u8DlcCurveDiffCoringTH; 158 MS_U8 u8DlcAlphaBlendingMin; 159 MS_U8 u8DlcAlphaBlendingMax; 160 MS_U8 u8DlcFlicker_alpha; 161 MS_U8 u8DlcYAVG_L_TH; 162 MS_U8 u8DlcYAVG_H_TH; 163 MS_U8 u8DlcDiffBase_L; 164 MS_U8 u8DlcDiffBase_M; 165 MS_U8 u8DlcDiffBase_H; 166 // NEW DLC 167 MS_U8 u8LMaxThreshold; 168 MS_U8 u8LMinThreshold; 169 MS_U8 u8LMaxCorrection; 170 MS_U8 u8LMinCorrection; 171 MS_U8 u8RMaxThreshold; 172 MS_U8 u8RMinThreshold; 173 MS_U8 u8RMaxCorrection; 174 MS_U8 u8RMinCorrection; 175 MS_U8 u8AllowLoseContrast; 176 } ST_KDRV_XC_DLC_INIT_INFO; 177 178 typedef struct 179 { 180 MS_U32 u32OutputNits[512]; 181 MS_U16 u16InputPoint[512]; 182 MS_U16 u16ControlPoints; 183 MS_S16 s16LastLess1IndexOutputnits; 184 MS_S16 s16LastIndexM10000Outputs; 185 MS_S16 s16LastIndexM100Outputs; 186 }ST_KDRV_XC_DLC_TMO_1DLUT; 187 188 189 // HDR new tone mapping parameters. 190 typedef struct 191 { 192 // TMO 193 MS_U16 u16SrcMinRatio; //default 10 194 MS_U16 u16SrcMedRatio; //default 512 195 MS_U16 u16SrcMaxRatio; //default 990 196 197 MS_U16 u16TgtMin; //default 500 198 MS_U16 u16TgtMed; 199 MS_U16 u16TgtMax; //default 300 200 201 MS_U16 u16FrontSlopeMin; //default 256 202 MS_U16 u16FrontSlopeMax; //default 512 203 MS_U16 u16BackSlopeMin; //default 128 204 MS_U16 u16BackSlopeMax; //default 256 205 206 MS_U16 u16SceneChangeThrd; //default 1024 207 MS_U16 u16SceneChangeRatioMax; //default 1024 208 209 MS_U8 u8IIRRatio; //default 31 210 MS_U8 u8TMOTargetMode; // default 0. 0 : keeps the value in initial function 1 : from output source 211 MS_U16 u16SDRPanelGain; // 212 213 MS_U16 u16Smin; 214 MS_U16 u16Smed; 215 MS_U16 u16Smax; 216 MS_U16 u16Tmin; 217 MS_U16 u16Tmed; 218 MS_U16 u16Tmax; 219 220 MS_BOOL bRefMode; 221 222 MS_U8 u8TMOUseIniControls; 223 ST_KDRV_XC_DLC_TMO_1DLUT stTMO1DLUT; 224 225 } ST_KDRV_XC_TMO_INFO; 226 227 //IO Ctrl struct defines: 228 typedef enum 229 { 230 E_KDRV_XC_HDR_NONE, 231 E_KDRV_XC_HDR_DOLBY, 232 E_KDRV_XC_HDR_OPEN, 233 E_KDRV_XC_HDR_TECHNICOLOR, 234 E_KDRV_XC_HDR_MAX, 235 } EN_KDRV_XC_HDR_TYPE; 236 237 typedef enum 238 { 239 E_KDRV_XC_INPUT_SOURCE_NONE, 240 E_KDRV_XC_INPUT_SOURCE_HDMI, 241 E_KDRV_XC_INPUT_SOURCE_OTT, 242 E_KDRV_XC_INPUT_SOURCE_MAX, 243 } EN_KDRV_XC_INPUT_SOURCE_TYPE; 244 245 typedef enum 246 { 247 E_KDRV_XC_AUTODOWNLOAD_CLIENT_HDR, 248 E_KDRV_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA, 249 E_KDRV_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA, 250 E_KDRV_XC_AUTODOWNLOAD_CLIENT_XVYCC, 251 E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE1, 252 E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE2, 253 E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE3, 254 E_KDRV_XC_AUTODOWNLOAD_CLIENT_DEMURA, 255 E_KDRV_XC_AUTODOWNLOAD_CLIENT_OP2LUT, 256 E_KDRV_XC_AUTODOWNLOAD_CLIENT_T3D_0, /// t3d of sc0 257 E_KDRV_XC_AUTODOWNLOAD_CLIENT_T3D_1, /// t3d of sc1 258 E_KDRV_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM, 259 E_KDRV_XC_AUTODOWNLOAD_CLIENT_FOOPM, 260 E_KDRV_XC_AUTODOWNLOAD_CLIENT_MAX, 261 } EN_KDRV_XC_AUTODOWNLOAD_CLIENT; 262 263 typedef enum 264 { 265 E_KDRV_XC_AUTODOWNLOAD_TRIGGER_MODE, 266 E_KDRV_XC_AUTODOWNLOAD_ENABLE_MODE, 267 } EN_KDRV_XC_AUTODOWNLOAD_MODE; 268 269 typedef enum 270 { 271 E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_TMO, 272 E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_3DLUT, 273 E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_GAMMA, 274 E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA, 275 } EN_KDRV_XC_AUTODOWNLOAD_SUB_CLIENT; 276 277 typedef enum 278 { 279 E_KDRV_XC_HDR_COLOR_NONE, 280 E_KDRV_XC_HDR_COLOR_YUV420, 281 E_KDRV_XC_HDR_COLOR_YUV422, 282 E_KDRV_XC_HDR_COLOR_YUV444, 283 E_KDRV_XC_HDR_COLOR_RGB, 284 E_KDRV_XC_HDR_COLOR_MAX, 285 } EN_KDRV_XC_HDR_COLOR_FORMAT; 286 287 typedef enum 288 { 289 E_KDRV_MLOAD_UNSUPPORTED = 0, 290 E_KDRV_MLOAD_DISABLED = 1, 291 E_KDRV_MLOAD_ENABLED = 2, 292 } EN_KDRV_MLOAD_TYPE; 293 294 typedef enum 295 { 296 E_CLIENT_MAIN_XC = 0, 297 E_CLIENT_MAIN_HDR = 1, 298 E_CLIENT_SUB_XC = 2, 299 E_CLIENT_SUB_HDR = 3, 300 E_CLIENT_MAX, 301 } EN_MLOAD_CLIENT_TYPE; 302 303 typedef enum 304 { 305 E_KDRV_MAIN_WINDOW = 0, 306 E_KDRV_SUB_WINDOW, 307 E_KDRV_MAX_WINDOW, 308 }EN_KDRV_WINDOW; 309 310 typedef enum 311 { 312 E_KDRV_XC = 0, 313 E_KDRV_HDR, 314 }EN_KDRV_DS_CLIENT_TYPE; 315 316 typedef enum 317 { 318 E_KDRV_XC_SC0 = 0, 319 E_KDRV_XC_SC1, 320 E_KDRV_XC_MAX, 321 }EN_KDRV_SC_DEVICE; 322 323 typedef enum 324 { 325 E_K_APIXC_RET_FAIL = 0, ///<Fail 326 E_K_APIXC_RET_OK, ///<OK 327 E_K_APIXC_RET_FAIL_FUN_NOT_SUPPORT, ///<Fail 328 E_K_APIXC_RET_FAIL_ENUM_NOT_SUPPORT, ///<Fail 329 E_K_APIXC_RET_FAIL_INVALID_PARAMETER, ///<Fail 330 } E_K_APIXC_ReturnValue; 331 332 typedef enum 333 { 334 E_K_XC_DS_INDEX_MVOP, 335 E_K_XC_DS_INDEX_SCALER, 336 E_K_XC_DS_INDEX_MAX, 337 }E_K_XC_DS_INDEX_SOURCE; 338 339 typedef struct 340 { 341 MS_U16 u16CMDCNT_IPM; 342 MS_U16 u16CMDCNT_IPS; 343 MS_U16 u16CMDCNT_OPM; 344 MS_U16 u16CMDCNT_OPS; 345 } K_XC_DS_CMDCNT; 346 347 typedef enum 348 { 349 E_MLOAD_TRIGGER_BY_OP_SYNC=0, 350 E_MLOAD_TRIGGER_BY_IP_MAIN_SYNC=1, 351 E_MLOAD_TRIGGER_BY_IP_SUB_SYNC=2, 352 E_MLOAD_TRIGGER_BY_SW=3, 353 E_MLOAD_TRIGGER_MAX, 354 } EN_MLOAD_TRIG_SYNC; 355 356 typedef struct __attribute__((packed)) 357 { 358 MS_U64 u64DS_Info_BaseAddr; ///< The memory base address to update IP/OP dynamic scaling registers. Absolute without any alignment. 359 MS_U8 u8MIU_Select; ///< 0: MIU0, 1: MIU1, etc. 360 MS_U8 u8DS_Index_Depth; ///< The index depth (how many entries to fire per MVOP Vsync falling) of DS 361 MS_BOOL bOP_DS_On; ///< OP dynamic scaling on/off 362 MS_BOOL bIPS_DS_On; ///< IPS dynamic scaling on/off 363 MS_BOOL bIPM_DS_On; ///< IPM dynamic scaling on/off 364 } K_XC_DynamicScaling_Info; 365 366 typedef enum 367 { 368 K_DS_IP, 369 K_DS_OP, 370 } k_ds_reg_ip_op_sel; 371 372 typedef enum 373 { 374 K_DS_XC, 375 K_DS_MVOP, 376 K_DS_GOP, 377 } k_ds_reg_source_sel; 378 379 //*****************DS NEW*****************// 380 typedef enum 381 { 382 E_DS_CLIENT_XC, 383 E_DS_CLIENT_HDR, 384 E_DS_CLIENT_PQ, 385 } E_DS_CLIENT; 386 387 typedef struct 388 { 389 E_DS_CLIENT client; 390 MS_U32 max_num; 391 } K_DS_register_info; 392 //****************************************// 393 typedef enum 394 { 395 // New 396 /// Initialize 397 E_KDRV_XC_CFD_CTRL_SET_INIT = 0, 398 /// VGA 399 E_KDRV_XC_CFD_CTRL_SET_VGA = 1, 400 /// TV (ATV) 401 E_KDRV_XC_CFD_CTRL_SET_TV = 2, 402 /// CVBS (AV) 403 E_KDRV_XC_CFD_CTRL_SET_CVBS = 3, 404 /// S-Video 405 E_KDRV_XC_CFD_CTRL_SET_SVIDEO = 4, 406 /// YPbPr 407 E_KDRV_XC_CFD_CTRL_SET_YPBPR = 5, 408 /// Scart 409 E_KDRV_XC_CFD_CTRL_SET_SCART = 6, 410 /// HDMI 411 E_KDRV_XC_CFD_CTRL_SET_HDMI = 7, 412 /// DTV 413 E_KDRV_XC_CFD_CTRL_SET_DTV = 8, 414 /// DVI 415 E_KDRV_XC_CFD_CTRL_SET_DVI = 9, 416 /// MM 417 E_KDRV_XC_CFD_CTRL_SET_MM = 10, 418 /// Panel 419 E_KDRV_XC_CFD_CTRL_SET_PANEL = 11, 420 /// HDR 421 E_KDRV_XC_CFD_CTRL_SET_HDR = 12, 422 /// EDID 423 E_KDRV_XC_CFD_CTRL_SET_EDID = 13, 424 /// OSD 425 E_KDRV_XC_CFD_CTRL_SET_OSD = 14, 426 /// Fire 427 E_KDRV_XC_CFD_CTRL_SET_FIRE = 15, 428 /// DLC 429 E_KDRV_XC_CFD_CTRL_SET_DLC = 16, 430 /// Linear RGB 431 E_KDRV_XC_CFD_CTRL_SET_LINEAR_RGB = 17, 432 /// Get CFD Output to HDMI Status and dicison. 433 E_KDRV_XC_CFD_CTRL_GET_HDMI_STATUS = 18, 434 /// Set force HDR Onoff or auto select setting 435 E_KDRV_XC_CFD_CTRL_SET_HDR_ONOFF_SETTING = 19, 436 /// Status 437 E_KDRV_XC_CFD_CTRL_GET_STATUS = 20, 438 /// TMO 439 E_KDRV_XC_CFD_CTRL_SET_TMO = 21, 440 /// Update Status 441 E_KDRV_XC_CFD_CTRL_UPDATE_STATUS = 22, 442 /// CFD CTRL_TYPE_EX start 443 /// (Set this base is 0x40000000 for int type) 444 E_KDRV_XC_CFD_CTRL_TYPE_EX_BASE = 0x40000000, 445 /// OSD_STATUS 446 E_KDRV_XC_CFD_CTRL_GET_OSD_PROCESS_CONFIGS = 0x40000001, 447 /// Max 448 E_KDRV_XC_CFD_CTRL_MAX, 449 } EN_KDRV_XC_CFD_CTRL_TYPE; 450 451 typedef struct __attribute__((packed)) 452 { 453 MS_U8* pu8Data; /// pointer to data 454 #if !defined (__aarch64__) 455 void *pDummy; 456 #endif 457 MS_U32 u32Size; /// data size 458 } ST_KDRV_XC_OPEN_METADATA_INFO; 459 460 typedef struct __attribute__((packed)) 461 { 462 MS_U8* pu8Data; /// pointer to data 463 #if !defined (__aarch64__) 464 void *pDummy; 465 #endif 466 MS_U32 u32Size; /// data size 467 } ST_KDRV_XC_3DLUT_INFO; 468 469 typedef struct 470 { 471 MS_U64 phyBaseAddr; /// baseaddr 472 MS_U32 u32Size; 473 MS_U32 u32MiuNo; 474 } ST_KDRV_XC_SHARE_MEMORY_INFO; 475 476 typedef struct 477 { 478 MS_U16 u16X; ///<start x of the window 479 MS_U16 u16Y; ///<start y of the window 480 MS_U16 u16Width; ///<width of the window 481 MS_U16 u16Height; ///<height of the window 482 } ST_KDRV_XC_WINDOW_INFO; 483 484 typedef struct 485 { 486 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enClient; /// current client 487 MS_U64 phyBaseAddr; /// baseaddr 488 MS_U32 u32Size; /// size 489 MS_U32 u32MiuNo; /// miu no 490 MS_BOOL bEnable; /// enable/disable the client 491 EN_KDRV_XC_AUTODOWNLOAD_MODE enMode; /// work mode 492 } ST_KDRV_XC_AUTODOWNLOAD_CONFIG_INFO; 493 494 typedef struct 495 { 496 EN_KDRV_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient; /// sub client 497 MS_BOOL bEnableRange; /// whether enable range, 0: write data to (0-511), 1: write data to (u32StartAddr-u16EndAddr) 498 MS_U16 u16StartAddr; /// start addr, range: 0-511, startaddr <= endaddr 499 MS_U16 u16EndAddr; /// end addr: range: 0-511, startaddr <= endaddr 500 } ST_KDRV_XC_AUTODOWNLOAD_FORMAT_INFO; 501 502 typedef struct __attribute__((packed)) 503 { 504 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enClient; /// current client 505 MS_U8* pu8Data; /// pointer to data 506 #if !defined (__aarch64__) 507 void *pDummy; 508 #endif 509 MS_U32 u32Size; /// data size 510 void* pParam; /// pointer to ST_KDRV_XC_AUTODOWNLOAD_FORMAT_INFO 511 #if !defined (__aarch64__) 512 void *pDummy2; 513 #endif 514 } ST_KDRV_XC_AUTODOWNLOAD_DATA_INFO; 515 516 typedef struct 517 { 518 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enClient; /// current client 519 MS_BOOL bSupported; /// whether it is supported 520 } ST_KDRV_XC_AUTODOWNLOAD_CLIENT_SUPPORTED_CAPS; 521 522 typedef struct 523 { 524 EN_MLOAD_CLIENT_TYPE _client_type; 525 MS_U64 PhyAddr; 526 MS_U32 u32BufByteLen; 527 } ST_KDRV_MLOAD_INIT; 528 529 typedef struct 530 { 531 EN_MLOAD_CLIENT_TYPE _client_type; 532 MS_BOOL bEnable; 533 } ST_KDRV_MLOAD_ENABLE; 534 535 typedef struct 536 { 537 EN_MLOAD_CLIENT_TYPE _client_type; 538 EN_KDRV_MLOAD_TYPE eReturn; 539 } ST_KDRV_MLOAD_GETSTATUS; 540 541 typedef struct 542 { 543 EN_MLOAD_CLIENT_TYPE _client_type; 544 MS_BOOL bImmeidate; 545 MS_BOOL bReturn; 546 } ST_KDRV_MLOAD_FIRE; 547 548 typedef struct 549 { 550 EN_MLOAD_CLIENT_TYPE _client_type; 551 MS_U32 u32Addr; 552 MS_U16 u16Data; 553 MS_U16 u16Mask; 554 MS_BOOL bReturn; 555 } ST_KDRV_MLOAD_WRT_CMD; 556 557 typedef struct 558 { 559 EN_MLOAD_CLIENT_TYPE _client_type; 560 MS_U32 u32Bank; 561 MS_U32 u32Addr; 562 MS_U16 u16Data; 563 MS_U16 u16Mask; 564 MS_BOOL bReturn; 565 } ST_KDRV_MLOAD_WRT_CMD_NONXC; 566 567 typedef struct 568 { 569 EN_MLOAD_CLIENT_TYPE _client_type; 570 MS_U16 u16train; 571 MS_U16 u16disp; 572 MS_BOOL bReturn; 573 } ST_KDRV_MLOAD_SET_IP_TRIG_P; 574 575 typedef struct 576 { 577 EN_MLOAD_CLIENT_TYPE _client_type; 578 MS_U16 *pu16Train; 579 MS_U16 *pu16Disp; 580 MS_BOOL bReturn; 581 } ST_KDRV_MLOAD_GET_IP_TRIG_P; 582 583 typedef struct 584 { 585 EN_MLOAD_CLIENT_TYPE _client_type; 586 EN_MLOAD_TRIG_SYNC eTriggerSync; 587 } ST_KDRV_MLOAD_SET_TRIG_SYNC; 588 589 typedef struct 590 { 591 EN_KDRV_SC_DEVICE u32DeviceID; 592 EN_KDRV_WINDOW eWindow; 593 E_K_APIXC_ReturnValue eReturn; 594 } ST_KDRV_DS_GET_DSForceIndexSupported; 595 596 typedef struct 597 { 598 EN_KDRV_SC_DEVICE u32DeviceID; 599 E_K_XC_DS_INDEX_SOURCE eDSIdxSrc; 600 EN_KDRV_WINDOW eWindow; 601 E_K_APIXC_ReturnValue eReturn; 602 } ST_KDRV_DS_SET_DSIndexSourceSelect; 603 604 typedef struct 605 { 606 EN_KDRV_SC_DEVICE u32DeviceID; 607 MS_BOOL bEnable; 608 MS_U8 u8Index; 609 EN_KDRV_WINDOW eWindow; 610 E_K_APIXC_ReturnValue eReturn; 611 } ST_KDRV_DS_SET_DSForceIndex; 612 613 typedef struct __attribute__((packed)) 614 { 615 EN_KDRV_SC_DEVICE u32DeviceID; 616 K_XC_DynamicScaling_Info *pstDSInfo; 617 #if !defined (__aarch64__) 618 MS_U32 pDummy; 619 #endif 620 MS_U32 u32DSInfoLen; 621 EN_KDRV_WINDOW eWindow; 622 MS_BOOL bReturn; 623 } ST_KDRV_DS_SetDynamicScaling; 624 625 typedef struct 626 { 627 EN_KDRV_SC_DEVICE u32DeviceID; 628 MS_BOOL bEnable; 629 } ST_KDRV_DS_SET_DynamicScalingFlag; 630 631 typedef struct 632 { 633 EN_KDRV_SC_DEVICE u32DeviceID; 634 MS_BOOL bReturn; 635 } ST_KDRV_DS_GetDynamicScalingStatus; 636 637 typedef struct 638 { 639 EN_KDRV_SC_DEVICE u32DeviceID; 640 MS_BOOL bEnable; 641 MS_BOOL bReturn; 642 } ST_KDRV_DS_EnableIPMTuneAfterDS; 643 644 typedef struct __attribute__((packed)) 645 { 646 EN_KDRV_SC_DEVICE u32DeviceID; 647 EN_KDRV_WINDOW eWindow; 648 E_DS_CLIENT client; 649 MS_U32 u32CmdRegAddr; 650 MS_U16 u16CmdRegValue; 651 k_ds_reg_ip_op_sel IPOP_Sel; 652 k_ds_reg_source_sel Source_Select; 653 K_XC_DS_CMDCNT *pstXC_DS_CmdCnt; 654 #if !defined (__aarch64__) 655 MS_U32 pDummy; 656 #endif 657 } ST_KDRV_DS_WriteSWDSCommand; 658 659 typedef struct __attribute__((packed)) 660 { 661 EN_KDRV_SC_DEVICE u32DeviceID; 662 EN_KDRV_WINDOW eWindow; 663 E_DS_CLIENT client; 664 MS_U32 u32Bank; 665 MS_U32 u32Addr; 666 MS_U16 u16Data; 667 MS_U16 u16Mask; 668 k_ds_reg_ip_op_sel IPOP_Sel; 669 K_XC_DS_CMDCNT *pstXC_DS_CmdCnt; 670 #if !defined (__aarch64__) 671 MS_U32 pDummy; 672 #endif 673 } ST_KDRV_DS_WriteSWDSCommandNonXC; 674 675 typedef struct __attribute__((packed)) 676 { 677 EN_KDRV_SC_DEVICE u32DeviceID; 678 EN_KDRV_WINDOW eWindow; 679 E_DS_CLIENT client; 680 MS_U32 u32CmdRegAddr; 681 MS_U16 u16CmdRegValue; 682 MS_U16 u16Mask; 683 k_ds_reg_ip_op_sel IPOP_Sel; 684 k_ds_reg_source_sel Source_Select; 685 K_XC_DS_CMDCNT *pstXC_DS_CmdCnt; 686 #if !defined (__aarch64__) 687 MS_U32 pDummy; 688 #endif 689 } ST_KDRV_DS_WriteSWDSCommand_Mask; 690 691 typedef struct __attribute__((packed)) 692 { 693 EN_KDRV_SC_DEVICE u32DeviceID; 694 EN_KDRV_WINDOW eWindow; 695 E_DS_CLIENT client; 696 k_ds_reg_ip_op_sel IPOP_Sel; 697 K_XC_DS_CMDCNT *pstXC_DS_CmdCnt; 698 #if !defined (__aarch64__) 699 MS_U32 pDummy; 700 #endif 701 } ST_KDRV_DS_Add_NullCommand; 702 703 typedef struct 704 { 705 EN_KDRV_SC_DEVICE u32DeviceID; 706 E_DS_CLIENT client; 707 MS_U32 max_num; 708 MS_BOOL bReturn; 709 } ST_KDRV_DS_SET_CLIENT; 710 711 typedef struct 712 { 713 MS_U8 u8SupportIndexNum; 714 } ST_KDRV_DS_GET_SUPPORT_INDEX_NUM; 715 716 typedef struct 717 { 718 EN_KDRV_SC_DEVICE u32DeviceID; 719 EN_KDRV_WINDOW eWindow; 720 MS_U8 u8DSIndex; 721 } ST_KDRV_DS_GET_INDEX_INFO; 722 723 typedef struct 724 { 725 EN_KDRV_SC_DEVICE u32DeviceID; 726 EN_KDRV_WINDOW eWindow; 727 } ST_KDRV_DS_FIRE_INDEX_INFO; 728 729 typedef struct 730 { 731 MS_U8 u8CurrentIndex; 732 MS_U64 phyRegAddr; // HDR register 733 MS_U32 u32RegSize; 734 MS_U64 phyLutAddr; // look-up table 735 MS_U32 u32LutSize; 736 MS_BOOL bDMEnable; 737 MS_BOOL bCompEnable; 738 } ST_KDRV_XC_DS_HDRInfo; 739 740 typedef struct __attribute__((packed)) 741 { 742 EN_KDRV_XC_CFD_CTRL_TYPE enCtrlType; 743 void *pParam; 744 #if !defined (__aarch64__) 745 void *pDummy; 746 #endif 747 MS_U32 u32ParamLen; //param length 748 MS_U16 u16ErrCode; 749 } ST_KDRV_XC_CFD_CONTROL_INFO; 750 /// CFD update status 751 typedef enum 752 { 753 E_KDRV_XC_CFD_STATUS_SYNC_GEN_BLACK_SCREEN_DISABLE, 754 E_KDRV_XC_CFD_STATUS_SYNC_GEN_BLACK_SCREEN_ENABLE, 755 ///MAX 756 E_KDRV_XC_CFD_STATUS_MAX 757 } EN_KDRV_XC_CFD_UPDATE_STATUS; 758 typedef struct 759 { 760 EN_KDRV_XC_CFD_UPDATE_STATUS enCFD_status; 761 } ST_KDRV_XC_CFD_UPDATE_STATUS; 762 763 //SWDR information 764 typedef struct __attribute__((packed)) 765 { 766 MS_BOOL bDRE_En; //1: enable; 0: disable 767 MS_BOOL bDRE_SWDR_En; //1: enable; 0: disable 768 MS_U8 u8DRE_DR_Set_BasicStrength; //default = 4, max = 32 769 MS_U8 u8DRE_SWDR_Set_BasicStrength; //default = 4, max = 32 770 MS_U16 u16DRE_SWDR_Set_StrengthDk; //dentity = 0x100; max = 0x200 771 MS_U16 u16DRE_SWDR_Set_StrengthBr; //dentity = 0x100; max = 0x200 772 MS_U8 u8DRE_SWDR_Set_SceneProtectLevel; //default = 0x08, max = 0x20 773 MS_U8 u8DRE_Set_TemporalFilterLevel; //default = 0x06, max = 0x20 774 MS_U8 u8DRE_Set_ColorCorrectLevel; //default = 0x10, max = 0x20 775 }ST_KDRV_XC_SWDR_INFO; 776 777 #endif //_MDRV_XC_ST_H 778