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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHVD.h 98 /// @brief HVD Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HVD_DEF_H_ 103 #define _DRV_HVD_DEF_H_ 104 105 #include "drvHVD_Common.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Driver Capability 109 //------------------------------------------------------------------------------------------------- 110 111 // HW capability 112 #define HVD_HW_SVD 1 113 #define HVD_HW_HVD 2 114 #if defined(CHIP_T2) 115 #define HVD_HW_VERSION HVD_HW_SVD 116 #else 117 #define HVD_HW_VERSION HVD_HW_HVD 118 #endif 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 // Feature switch 124 #if defined(REDLION_LINUX_KERNEL_ENVI) 125 #define HVD_ENABLE_MUTEX_PROTECT 0 126 #define HVD_ENABLE_MIU_RST_PROTECT 1 127 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 128 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 129 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 130 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 131 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 132 #define HVD_ENABLE_MSOS_MIU1_BASE 0 133 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 134 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 135 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 136 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 137 #define HVD_ENABLE_TIME_MEASURE 0 138 #define HVD_ENABLE_REINIT_FAILED 1 139 #define HVD_ENABLE_RV_FEATURE 0 140 #else 141 #define HVD_ENABLE_MUTEX_PROTECT 1 142 #define HVD_ENABLE_MIU_RST_PROTECT 1 143 #if 1//defined( MSOS_TYPE_LINUX) 144 #define HVD_ENABLE_AUTO_SET_REG_BASE 1 145 #else 146 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 147 #endif 148 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) 149 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 150 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 151 #else 152 #define HVD_ENABLE_PATCH_ISFRAMERDY 1 153 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 154 #endif 155 #if defined(MSOS_TYPE_NOS) && (defined(CHIP_T3) || defined(CHIP_T8) || defined(CHIP_J2)) 156 #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 157 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 158 #else 159 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 160 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 161 #endif 162 163 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 164 165 #if defined(CHIP_JANUS) 166 #define HVD_ENABLE_MSOS_MIU1_BASE 0 167 #else 168 #define HVD_ENABLE_MSOS_MIU1_BASE 1 169 #endif 170 171 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 172 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 173 #define HVD_ENABLE_TIME_MEASURE 0 174 #define HVD_ENABLE_REINIT_FAILED 0 175 176 #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) 177 #define HVD_ENABLE_RV_FEATURE 0 178 #else 179 #define HVD_ENABLE_RV_FEATURE 1 180 #endif 181 182 #if defined(CHIP_T12) || \ 183 defined(CHIP_J2) || \ 184 defined(CHIP_A1) || \ 185 defined(CHIP_A2) || \ 186 defined(CHIP_A5) || \ 187 defined(CHIP_A5P) || \ 188 defined(CHIP_A7) || \ 189 defined(CHIP_A3) || \ 190 defined(CHIP_AMETHYST)|| \ 191 defined(CHIP_AGATE) || \ 192 defined(CHIP_EDISON) || \ 193 defined(CHIP_EMERALD)|| \ 194 defined(CHIP_EAGLE) || \ 195 defined(CHIP_EIFFEL) || \ 196 defined(CHIP_NIKE) || \ 197 defined(CHIP_MADISON) || \ 198 defined(CHIP_CLIPPERS) || \ 199 defined(CHIP_MIAMI) || \ 200 defined(CHIP_NUGGET) || \ 201 defined(CHIP_KAISER) || \ 202 defined(CHIP_NIKON) || \ 203 defined(CHIP_EINSTEIN)|| \ 204 defined(CHIP_NAPOLI) || \ 205 defined(CHIP_KERES) || \ 206 defined(CHIP_MONACO) || \ 207 defined(CHIP_MUNICH) 208 #define HVD_ENABLE_MVC 1 209 #else 210 #define HVD_ENABLE_MVC 0 211 #endif 212 213 #endif 214 215 #if defined(REDLION_LINUX_KERNEL_ENVI) 216 #include "drvHVD_redlion.h" 217 #endif 218 219 #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) 220 #include "osalHVD_EX.h" 221 #endif 222 223 #if HVD_ENABLE_MSOS_MIU1_BASE 224 #include "halCHIP.h" 225 #endif 226 227 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF 228 #include "drvBDMA.h" 229 #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) 230 #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) 231 #endif 232 233 // debug switch 234 // DEBUG 235 #if defined (REDLION_LINUX_KERNEL_ENVI) 236 #define HVD_PRINT printk 237 #define HVD_ERR printk 238 #elif defined (ANDROID) 239 #include <sys/mman.h> 240 #include <cutils/ashmem.h> 241 #include <cutils/log.h> 242 #ifndef LOGI // android 4.1 rename LOGx to ALOGx 243 #define HVD_PRINT ALOGI 244 #else 245 #define HVD_PRINT LOGI 246 #endif 247 #ifndef LOGE // android 4.1 rename LOGx to ALOGx 248 #define HVD_ERR ALOGE 249 #else 250 #define HVD_ERR LOGE 251 #endif 252 #else 253 #define HVD_PRINT printf 254 #define HVD_ERR printf 255 #endif 256 257 #define HVD_EX_MSG_MUST(format, args...) \ 258 do \ 259 { \ 260 if (u32UartCtrl & E_HVD_UART_CTRL_MUST) \ 261 { \ 262 HVD_ERR("[HVD][MUST]%s:", __FUNCTION__); \ 263 HVD_ERR(format, ##args); \ 264 } \ 265 } while (0) 266 267 #define HVD_EX_MSG_ERR(format, args...) \ 268 do \ 269 { \ 270 if (u32UartCtrl & E_HVD_UART_CTRL_ERR) \ 271 { \ 272 HVD_ERR("[HVD][ERR]%s:", __FUNCTION__); \ 273 HVD_ERR(format, ##args); \ 274 } \ 275 } while (0) 276 277 #if ((defined(CHIP_A1) || defined(CHIP_A7) || defined(CHIP_AMETHYST) || defined(CHIP_EMERALD) || defined(CHIP_NUGGET) || defined(CHIP_NIKON)) && defined (__aeon__)) 278 #define HVD_EX_MSG_INF(format, args...) 279 #define HVD_EX_MSG_DBG(format, args...) 280 #define HVD_EX_MSG_TRACE() 281 #else 282 #define HVD_EX_MSG_INF(format, args...) \ 283 do \ 284 { \ 285 if (u32UartCtrl & E_HVD_UART_CTRL_INFO) \ 286 { \ 287 HVD_PRINT("[HVD][INF]%s:", __FUNCTION__); \ 288 HVD_PRINT(format, ##args); \ 289 } \ 290 } while (0) 291 292 #define HVD_EX_MSG_DBG(format, args...) \ 293 do \ 294 { \ 295 if (u32UartCtrl & E_HVD_UART_CTRL_DBG) \ 296 { \ 297 HVD_PRINT("[HVD][DBG]%s:", __FUNCTION__); \ 298 HVD_PRINT(format, ##args); \ 299 } \ 300 } while (0) 301 302 #define HVD_EX_MSG_TRACE() \ 303 do \ 304 { \ 305 if (u32UartCtrl & E_HVD_UART_CTRL_TRACE) \ 306 { \ 307 HVD_PRINT("[HVD][TRA]%s:", __FUNCTION__); \ 308 } \ 309 } while (0) 310 #endif 311 312 // Configs 313 #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks 314 #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 315 316 #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 317 318 319 // Util or Functions 320 #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) 321 #define HVD_LWORD(x) (MS_U16)((x)&0xffff) 322 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) 323 #define HVD_U32_MAX 0xffffffffUL 324 #define HVD_RV_BROKENBYUS_MASK 0x00800000 325 326 #ifdef MSOS_TYPE_LINUX 327 #if HVD_ENABLE_MSOS_SYSTEM_CALL 328 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 329 #else 330 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 331 #endif 332 #else 333 #define HVD_VA2PA(x) (x) 334 #endif 335 336 #if defined(REDLION_LINUX_KERNEL_ENVI) 337 #define HVD_PA2VA(x ) (MS_U32)MDrv_SYS_PA2NonCacheSeg((void*)(x)) 338 #else 339 #define HVD_PA2VA(x ) (MS_U32)MS_PA2KSEG1((MS_U32)(x)) 340 #endif 341 342 #if 0//def memcpy 343 #define HVD_memcpy(x , y , z) memcpy(x, y, z) 344 #else 345 346 #if 0 347 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 348 do { \ 349 MS_U32 i = 0; \ 350 volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ 351 volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ 352 for (i = 0; i < (u32Size); i++) \ 353 { \ 354 Dest[i] = Src[i]; \ 355 } \ 356 }while(0) 357 #else 358 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 359 do { \ 360 register unsigned long u32I=0; \ 361 register unsigned long u32Dst = (unsigned long)pDstAddr; \ 362 void * pSrc = (void *)pSrcAddr; \ 363 MS_U32 _u32memsize = u32Size; \ 364 if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ 365 { \ 366 for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ 367 { \ 368 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 369 } \ 370 } \ 371 else \ 372 { \ 373 for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ 374 { \ 375 ((volatile unsigned long *)u32Dst)[u32I] = ((volatile unsigned long *)pSrc)[u32I]; \ 376 } \ 377 if((_u32memsize)%4) \ 378 { \ 379 u32Dst += u32I*4; \ 380 pSrc = (void *)((unsigned long)pSrc + u32I*4); \ 381 for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ 382 { \ 383 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 384 } \ 385 } \ 386 } \ 387 }while(0) 388 #endif 389 390 #endif 391 392 393 394 #if HVD_ENABLE_MSOS_SYSTEM_CALL 395 #define HVD_Delay_ms(x) MsOS_DelayTask(x) 396 #define HVD_SYSTEM_DELAY_MS_TYPE 2 397 #elif defined(REDLION_LINUX_KERNEL_ENVI) 398 #define HVD_Delay_ms(x) msleep(x) 399 //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) 400 #define HVD_SYSTEM_DELAY_MS_TYPE 3 401 #else 402 #define HVD_Delay_ms(x) \ 403 do { \ 404 volatile MS_U32 ticks=0; \ 405 while( ticks < ( ((MS_U32)(x)) <<13) ) \ 406 { \ 407 ticks++; \ 408 } \ 409 } while(0) 410 #define HVD_SYSTEM_DELAY_MS_TYPE 0 411 #endif // HVD_ENABLE_MSOS_SYSTEM_CALL 412 413 414 #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ 415 do{ \ 416 MS_U32 i = 0; \ 417 MS_U32 j = 0; \ 418 MS_U8* temp = (MS_U8*)addr; \ 419 MS_U8 string[17] ; \ 420 HVD_EX_MSG_DBG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ 421 temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ 422 memset(string , 0 , sizeof(string)); \ 423 for (j = 0; j < (size >> 4); j++) \ 424 { \ 425 if (ascii) \ 426 { \ 427 for (i = 0; i < 16; i++) \ 428 { \ 429 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 430 string[i] = *(temp + i); \ 431 else \ 432 string[i] = '.'; \ 433 } \ 434 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ 435 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ 436 } \ 437 else \ 438 { \ 439 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ 440 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ 441 } \ 442 temp += 16; \ 443 } \ 444 HVD_EX_MSG_DBG("0x%08x " , j << 4); \ 445 memset(string , 0 , sizeof(string)); \ 446 for (i = 0; i < (size & 0x0f); i++) \ 447 { \ 448 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 449 string[i] = *(temp + i); \ 450 else \ 451 string[i] = '.'; \ 452 HVD_EX_MSG_DBG("%02x ", *(MS_U8*)(temp + i)); \ 453 } \ 454 if (ascii) \ 455 { \ 456 for (; i < 16 ; i++) \ 457 HVD_EX_MSG_DBG(" "); \ 458 HVD_EX_MSG_DBG(" %s\n" , string); \ 459 } \ 460 else \ 461 HVD_EX_MSG_DBG("\n"); \ 462 }while(0) 463 464 465 #if HVD_ENABLE_MSOS_SYSTEM_CALL 466 #define HVD_GetSysTime_ms() MsOS_GetSystemTime() 467 #define HVD_SYSTEM_CLOCK_TYPE 1 468 #elif defined(REDLION_LINUX_KERNEL_ENVI) 469 #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() 470 #define HVD_SYSTEM_CLOCK_TYPE 2 471 #else 472 #define HVD_GetSysTime_ms() 1 473 #define HVD_SYSTEM_CLOCK_TYPE 0 474 #endif // MsOS_GetSystemTime 475 476 #if HVD_ENABLE_MSOS_SYSTEM_CALL 477 #include "asmCPU.h" 478 #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() 479 #define HVD_MEMORY_BARRIER_TYPE 3 480 #else 481 #if defined (__mips__) 482 #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") 483 #define HVD_MEMORY_BARRIER_TYPE 1 484 #elif defined (__aeon__) 485 #ifdef __AEONR2__ 486 #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") 487 #define HVD_MEMORY_BARRIER_TYPE 22 488 #else 489 #if defined( CHIP_T2 ) 490 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") 491 #define HVD_MEMORY_BARRIER_TYPE 21 492 #else 493 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") 494 #define HVD_MEMORY_BARRIER_TYPE 23 495 #endif 496 #endif 497 #else 498 #define HAL_MEMORY_BARRIER() 499 #define HVD_MEMORY_BARRIER_TYPE 0 500 #endif 501 #endif 502 503 #define HVD_DRV_MODE_EXTERNAL_DS_BUFFER (1 << 0) 504 505 //------------------------------------------------------------------------------------------------- 506 // Type and Structure 507 //------------------------------------------------------------------------------------------------- 508 typedef void (*HVD_ISRCallBack)(MS_U32 u32Sid); 509 510 typedef enum 511 { 512 E_HVD_RETURN_FAIL=0, 513 E_HVD_RETURN_SUCCESS, 514 E_HVD_RETURN_INVALID_PARAMETER, 515 E_HVD_RETURN_ILLEGAL_ACCESS, 516 E_HVD_RETURN_HARDWARE_BREAKDOWN, 517 E_HVD_RETURN_OUTOF_MEMORY, 518 E_HVD_RETURN_UNSUPPORTED, 519 E_HVD_RETURN_TIMEOUT, 520 E_HVD_RETURN_NOTREADY, 521 E_HVD_RETURN_MEMORY_OVERWIRTE, 522 E_HVD_RETURN_ES_FULL, 523 E_HVD_RETURN_RE_INIT, 524 E_HVD_RETURN_NOT_RUNNING, 525 } HVD_Return; 526 527 typedef enum 528 { 529 // share memory 530 E_HVD_GDATA_SHARE_MEM=0x1000, 531 // switch 532 //E_HVD_GDATA_SEMAPHORE, 533 E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), 534 // report 535 E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), 536 E_HVD_GDATA_U64PTS, 537 E_HVD_GDATA_DECODE_CNT, 538 E_HVD_GDATA_DATA_ERROR_CNT, 539 E_HVD_GDATA_DEC_ERROR_CNT, 540 E_HVD_GDATA_ERROR_CODE, 541 E_HVD_GDATA_VPU_IDLE_CNT, 542 E_HVD_GDATA_DISP_FRM_INFO, 543 E_HVD_GDATA_DEC_FRM_INFO, 544 E_HVD_GDATA_ES_LEVEL, 545 E_HVD_GDATA_PTS_STC_DIFF, 546 #if HVD_ENABLE_MVC 547 E_HVD_GDATA_DISP_FRM_INFO_SUB, 548 E_HVD_GDATA_DEC_FRM_INFO_SUB, 549 #endif 550 E_HVD_GDATA_HVD_HW_MAX_PIXEL, 551 552 // user data 553 E_HVD_GDATA_USERDATA_WPTR, 554 E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, 555 E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, 556 E_HVD_GDATA_USERDATA_PACKET_SIZE, 557 E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, 558 E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, 559 // report - modes 560 E_HVD_GDATA_IS_SHOW_ERR_FRM, 561 E_HVD_GDATA_IS_REPEAT_LAST_FIELD, 562 E_HVD_GDATA_IS_ERR_CONCEAL, 563 E_HVD_GDATA_IS_SYNC_ON, 564 E_HVD_GDATA_IS_PLAYBACK_FINISH, 565 E_HVD_GDATA_SYNC_MODE, 566 E_HVD_GDATA_SKIP_MODE, 567 E_HVD_GDATA_DROP_MODE, 568 E_HVD_GDATA_DISPLAY_DURATION, 569 E_HVD_GDATA_FRC_MODE, 570 E_HVD_GDATA_NEXT_PTS, 571 E_HVD_GDATA_DISP_Q_SIZE, 572 E_HVD_GDATA_DISP_Q_PTR, 573 E_HVD_GDATA_NEXT_DISP_FRM_INFO, 574 E_HVD_GDATA_REAL_FRAMERATE, 575 E_HVD_GDATA_IS_ORI_INTERLACE_MODE, 576 E_HVD_GDATA_FRM_PACKING_SEI_DATA, 577 E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, 578 E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE, 579 E_HVD_GDATA_FIELD_PIC_FLAG, 580 E_HVD_GDATA_FW_STATUS_FLAG, 581 582 // internal control 583 E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), 584 E_HVD_GDATA_IS_I_FRM_FOUND, 585 E_HVD_GDATA_IS_SYNC_START, 586 E_HVD_GDATA_IS_SYNC_REACH, 587 E_HVD_GDATA_FW_VERSION_ID, 588 E_HVD_GDATA_FW_IF_VERSION_ID, 589 E_HVD_GDATA_BBU_Q_NUMB, 590 E_HVD_GDATA_DEC_Q_NUMB, 591 E_HVD_GDATA_DISP_Q_NUMB, 592 E_HVD_GDATA_PTS_Q_NUMB, 593 E_HVD_GDATA_FW_INIT_DONE, 594 E_HVD_GDATA_FW_IS_IQMEM_SUPPORT, 595 E_HVD_GDATA_FW_IQMEM_CTRL, 596 E_HVD_GDATA_FW_FLUSH_STATUS, 597 E_HVD_GDATA_FW_CODEC_TYPE, 598 E_HVD_GDATA_FW_ES_BUF_STATUS, 599 E_HVD_GDATA_TS_SEAMLESS_STATUS, 600 601 // debug 602 E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), 603 E_HVD_GDATA_GOP_CNT, 604 E_HVD_GDATA_DISP_CNT, 605 E_HVD_GDATA_DROP_CNT, 606 E_HVD_GDATA_DISP_STC, 607 E_HVD_GDATA_VSYNC_CNT, 608 E_HVD_GDATA_MAIN_LOOP_CNT, 609 // AVC 610 E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), 611 E_HVD_GDATA_AVC_LOW_DELAY, 612 E_HVD_GDATA_AVC_VUI_DISP_INFO, 613 //E_HVD_GDATA_AVC_SPS_ADDR, 614 615 // SRAM 616 E_HVD_GDATA_SRAM=0x2000, 617 //E_HVD_GDATA_AVC_NAL_CNT, 618 619 // Mailbox or Reg 620 E_HVD_GDATA_MBOX=0x3000, 621 E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) 622 E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) 623 E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) 624 E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) 625 E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) 626 E_HVD_GDATA_ES_READ_PTR, // 627 E_HVD_GDATA_ES_WRITE_PTR, // 628 E_HVD_GDATA_BBU_READ_PTR, // 629 E_HVD_GDATA_BBU_WRITE_PTR, // 630 E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // 631 E_HVD_GDATA_VPU_PC_CNT, // 632 E_HVD_GDATA_ES_QUANTITY, 633 634 // FW def 635 E_HVD_GDATA_FW_DEF=0x4000, 636 E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? 637 E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, 638 E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, 639 E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, 640 E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, 641 E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, 642 E_HVD_GDATA_FW_DS_BUF_ADDR, 643 E_HVD_GDATA_FW_DS_BUF_SIZE, 644 E_HVD_GDATA_FW_DS_VECTOR_DEPTH, 645 E_HVD_GDATA_FW_DS_INFO_ADDR, 646 E_HVD_GDATA_FW_DS_IS_ENABLED, 647 E_HVD_GDATA_FW_VSYNC_BRIDGE_ADDR, 648 // BBU size 649 // default pitch number 650 // 651 } HVD_GetData; 652 653 typedef enum 654 { 655 // share memory 656 E_HVD_SDATA_SHARE_MEM = 0x1000, 657 // switch 658 E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100 + E_HVD_SDATA_SHARE_MEM), 659 E_HVD_SDATA_FRAMEBUF_SIZE, 660 E_HVD_SDATA_ERROR_CODE, 661 E_HVD_SDATA_DISP_INFO_TH, 662 E_HVD_SDATA_FW_FLUSH_STATUS, 663 E_HVD_SDATA_DMX_FRAMERATE, 664 E_HVD_SDATA_DMX_FRAMERATEBASE, 665 E_HVD_SDATA_MIU_SEL, 666 // display info 667 //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), 668 // report 669 //E_HVD_SDATA_PTS=0x0200, 670 // internal control 671 //E_HVD_SDATA_IDLE_CNT=0x0300, 672 // debug 673 //E_HVD_SDATA_SKIP_CNT=0x0400, 674 // RM 675 E_HVD_SDATA_RM_PICTURE_SIZES = (0x0500 | E_HVD_SDATA_SHARE_MEM), 676 677 // SRAM 678 // Mailbox or Reg 679 E_HVD_SDATA_MAILBOX = 0x3000, 680 E_HVD_SDATA_FW_CODE_TYPE = (0x0000 | E_HVD_SDATA_MAILBOX), 681 E_HVD_SDATA_TRIGGER_DISP, 682 E_HVD_SDATA_GET_DISP_INFO_DONE, 683 E_HVD_SDATA_GET_DISP_INFO_START, 684 685 // FW def 686 E_HVD_SDATA_FW_DEF = 0x4000, 687 E_HVD_SDATA_VIRTUAL_BOX_WIDTH, 688 E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, 689 //modify the state of the frame in DispQueue 690 E_HVD_SDATA_DISPQ_STATUS_VIEW, 691 E_HVD_SDATA_DISPQ_STATUS_DISP, 692 E_HVD_SDATA_DISPQ_STATUS_FREE, 693 E_HVD_SDATA_FW_IQMEM_CTRL, 694 E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, 695 } HVD_SetData; 696 697 typedef enum 698 { 699 E_HVD_UART_CTRL_DISABLE = BIT(4), 700 E_HVD_UART_CTRL_ERR = BIT(0), 701 E_HVD_UART_CTRL_INFO = BIT(1), 702 E_HVD_UART_CTRL_DBG = BIT(2), 703 E_HVD_UART_CTRL_FW = BIT(3), 704 E_HVD_UART_CTRL_MUST = BIT(4), 705 E_HVD_UART_CTRL_TRACE = BIT(5), 706 } HVD_Uart_Ctrl; 707 708 typedef enum 709 { 710 E_HVD_INIT_HW_MASK = BMASK(3:0), ///< HW Type, should same as HVD_Codec_Type in fwHVD_if.h 711 E_HVD_INIT_HW_AVC = BITS(3:0, 0), ///< HW deflaut: AVC 0X00 712 E_HVD_INIT_HW_AVS = BITS(3:0, 1), ///< HW: AVS 0X01 713 E_HVD_INIT_HW_RM = BITS(3:0, 2), ///< HW: RM 0X10 714 E_HVD_INIT_HW_MVC = BITS(3:0, 3), ///< HW: MVC 0x11 715 E_HVD_INIT_HW_VP8 = BITS(3:0, 4), ///< HW: VP8 0X100 716 E_HVD_INIT_HW_MJPEG = BITS(3:0, 5), ///< HW: MJPEG 0x101 717 E_HVD_INIT_HW_VP6 = BITS(3:0, 6), ///< HW: VP6 0x110 718 E_HVD_INIT_HW_HEVC = BITS(3:0, 7), ///< HW: HEVC 0x111 719 E_HVD_INIT_HW_VP9 = BITS(3:0, 8), ///< HW: VP9 0x1000 720 E_HVD_INIT_MAIN_MASK = BMASK(5:4), ///< main type 721 E_HVD_INIT_MAIN_FILE_RAW = BITS(5:4, 0), ///< main type: default: 0X00 722 E_HVD_INIT_MAIN_FILE_TS = BITS(5:4, 1), ///< main type: 0X01 723 E_HVD_INIT_MAIN_LIVE_STREAM = BITS(5:4, 2), ///< main type: 0X10 724 E_HVD_INIT_INPUT_MASK = BMASK(6:6), ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode 725 E_HVD_INIT_INPUT_TSP = BITS(6:6, 0), ///< tsp input( default) 726 E_HVD_INIT_INPUT_DRV = BITS(6:6, 1), ///< driver input 727 E_HVD_INIT_START_CODE_MASK = BMASK(7:7), ///< AVC FILE MODE ONLY: mkv, mp4 container use. 728 E_HVD_INIT_START_CODE_REMAINED = BITS(7:7, 0), ///< start code remained.(Defualt) 729 E_HVD_INIT_START_CODE_REMOVED = BITS(7:7, 1), ///< start code removed. 730 E_HVD_INIT_UTOPIA_ENVI = BIT(8), ///< check MIU sel and set it 731 E_HVD_INIT_DBG_FW = BIT(9), ///< check FW is debug version or not 732 E_HVD_INIT_DUAL_ES_MASK = BMASK(10:10), ///< Dual ES buffer iput. 733 E_HVD_INIT_DUAL_ES_DISABLE = BITS(10:10, 0), ///< Disable Dual ES buffer input. 734 E_HVD_INIT_DUAL_ES_ENABLE = BITS(10:10, 1), ///< Enable Dual ES buffer input. 735 //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. 736 } HVD_Init_Mode_Flag; 737 738 typedef enum 739 { 740 E_HVD_PLAY_NORMAL, 741 E_HVD_PLAY_PAUSE, 742 E_HVD_PLAY_STEP_DISPLAY, 743 } HVD_Play_Type; 744 745 typedef enum 746 { 747 E_HVD_ESB_LEVEL_NORMAL = 0, 748 E_HVD_ESB_LEVEL_UNDER = BIT(0), 749 E_HVD_ESB_LEVEL_OVER = BIT(1), 750 } HVD_ESBuf_Level; 751 752 //----------------------------------------------------------------------------- 753 /// @brief \b Enum \b Name: HVD_FWInputSourceType 754 /// @brief \b Enum \b Description: The type of fw binary input source 755 //----------------------------------------------------------------------------- 756 typedef enum 757 { 758 E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. 759 E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. 760 E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. 761 } HVD_FWInputSourceType; 762 763 //----------------------------------------------------------------------------- 764 /// @brief \b Enum \b Name: HVD_FB_Reduction_Type 765 /// @brief \b Enum \b Description: The type of frame buffer reduction type 766 //----------------------------------------------------------------------------- 767 typedef enum 768 { 769 E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable 770 E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 771 E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 772 } HVD_FBReductionType; 773 774 typedef enum 775 { 776 E_VDEC_EX_MAIN_VIEW = 0, ///< MVC main view 777 E_VDEC_EX_SUB_VIEW, ///< MVC sub view 778 } VDEC_EX_View; 779 780 typedef enum 781 { 782 E_HVD_SECURE_MODE_NONE = 0, /// None secure 783 E_HVD_SECURE_MODE_TRUSTZONE /// Secure for TrustZone 784 } HVD_SECURE_MODE; 785 786 //----------------------------------------------------------------------------- 787 /// @brief \b Struct \b Name: HVD_EX_MemMap 788 /// @brief \b Struct \b Description: Store the HVD driver config 789 //----------------------------------------------------------------------------- 790 typedef struct 791 { 792 MS_U32 u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. 793 MS_U32 u32MIU2BaseAddr; //!< the physical memory start address of MIU 2 base address. 0: default value. 794 MS_U32 u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM 795 MS_U32 u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. 796 MS_U32 u32FWBinarySize; //!< the FW code size 797 MS_U32 u32VLCBinaryVAddr; ///< VLC table binary data buffer start address 798 MS_U32 u32VLCBinaryAddr; ///< VLC table binary data buffer start address 799 MS_U32 u32VLCBinarySize; ///<VLC table binary data buffer size 800 MS_U32 u32CodeBufVAddr; //!< the virtual memory start address of code buffer 801 MS_U32 u32CodeBufAddr; //!< the physical memory start address of code buffer 802 MS_U32 u32CodeBufSize; //!< the code buffer size 803 MS_U32 u32FrameBufVAddr; //!< the virtual memory start address of frame buffer 804 MS_U32 u32FrameBufAddr; //!< the physical memory start address of frame buffer 805 MS_U32 u32FrameBufSize; //!< the frame buffer size 806 MS_U32 u32BitstreamBufVAddr; //!< the virtual memory start address of bit stream buffer 807 MS_U32 u32BitstreamBufAddr; //!< the physical memory start address of bit stream buffer 808 MS_U32 u32BitstreamBufSize; //!< the bit stream buffer size 809 MS_U32 u32DrvProcessBufVAddr; //!< the virtual memory start address of driver process buffer 810 MS_U32 u32DrvProcessBufAddr; //!< the physical memory start address of driver process buffer 811 MS_U32 u32DrvProcessBufSize; //!< the driver process buffer size 812 MS_U32 u32DynSacalingBufVAddr; //!< the virtual memory start address of dynamic scaling buffer 813 MS_U32 u32DynSacalingBufAddr; //!< the physical memory start address of dynamic scaling buffer 814 MS_U32 u32DynSacalingBufSize; //!< the dynamic scaling buffer size 815 HVD_FWInputSourceType eFWSourceType; //!< the input FW source type. 816 } HVD_EX_MemMap; 817 818 //----------------------------------------------------------------------------- 819 /// @brief \b Struct \b Name: HVD_Nal_Entry 820 /// @brief \b Struct \b Description: Store the information of one nal entry 821 //----------------------------------------------------------------------------- 822 typedef struct 823 { 824 MS_U32 u32NalID; ///< the ID nunber of this nal 825 MS_U32 u32NalAddr; ///< the offset of this nal from bit stream buffer start address. unit: byte 826 MS_U32 u32NalSize; ///< the size of this nal. unit: byte 827 MS_U32 u32NalPTS; ///< the time stamp of this nal. unit: ms 828 MS_BOOL bRVBrokenPacket; ///< the RV only 829 } HVD_Nal_Entry; 830 831 //----------------------------------------------------------------------------- 832 /// @brief \b Struct \b Name: RV_FileInfo 833 /// @brief \b Struct \b Description: RV file information 834 //----------------------------------------------------------------------------- 835 typedef struct 836 { 837 MS_U16 RV_Version; ///< Real Video Bitstream version 838 MS_U16 ulNumSizes; ///< Real Video Number sizes 839 MS_U16 ulPicSizes_w[8]; ///< Real Video file width 840 MS_U16 ulPicSizes_h[8]; ///< Real Video file height 841 } RV_FileInfo; 842 843 //----------------------------------------------------------------------------- 844 /// @brief \b Struct \b Name: HVD_FB_Reduction_Mode 845 /// @brief \b Struct \b Description: Set up frame buffer reduction mode 846 //----------------------------------------------------------------------------- 847 typedef struct 848 { 849 HVD_FBReductionType eLumaFBReductionMode; ///< Luma frame buffer reduction mode. 850 HVD_FBReductionType eChromaFBReductionMode; ///< Chroma frame buffer reduction mode. 851 MS_U8 u8EnableAutoMode; /// 0: Disable, 1: Enable 852 } HVD_FBReductionMode; 853 854 //----------------------------------------------------------------------------- 855 /// @brief \b Struct \b Name: HVD_Init_Params 856 /// @brief \b Struct \b Description: Store the initialization settings 857 //----------------------------------------------------------------------------- 858 typedef struct 859 { 860 MS_U32 u32ModeFlag; ///< init mode flag, use HVD_INIT_* to setup HVD. 861 MS_U32 u32FrameRate; ///< frame rate. 862 MS_U32 u32FrameRateBase; ///< frame rate base. The value of u32FrameRate /u32FrameRateBase must be frames per sec. 863 MS_U8 u8MinFrmGap; ///< set the min frame gap. 864 MS_U8 u8SyncType; ///< HVD_EX_SyncType. sync type of current playback. 865 MS_U16 u16Pitch; ///< not zero: specify the pitch. 0: use default value. 866 MS_U32 u32MaxDecTick; ///< not zero: specify the max decode tick. 0: use default value. 867 MS_BOOL bSyncEachFrm; ///< TRUE: sync STC at each frame. FALSE: not sync each frame. 868 MS_BOOL bAutoFreeES; ///< TRUE: auto free ES buffer when ES buffer is full. FALSE: not do the auto free. 869 MS_BOOL bAutoPowerSaving; ///< TRUE: auto power saving. FALSE: not do the auto power saving. 870 MS_BOOL bDynamicScaling; ///< TRUE: enable Dynamic Scaling. FALSE: disable Dynamic Scaling. 871 MS_BOOL bFastDisplay; ///< TRUE: enable Fast Display. FALSE: disable Fast Display. 872 MS_BOOL bUserData; ///< TRUE: enable processing User data. FALSE: disable processing User data. 873 MS_U8 u8TurboInit; ///< HVD_TurboInitLevel. set the turbo init mode. 874 MS_U8 u8TimeUnit; ///< HVD_Time_Unit_Type.set the type of input/output time unit. 875 MS_U16 u16DecoderClock; ///< HVD decoder clock speed. 0: default value. non-zero: any nearist clock. 876 MS_U16 u16ChipECONum; ///< Chip revision, ECO number. 877 RV_FileInfo* pRVFileInfo; ///< pointer to RV file info 878 HVD_FBReductionMode stFBReduction; ///< HVD Frame buffer reduction type 879 } HVD_Init_Params; 880 881 //----------------------------------------------------------------------------- 882 /// @brief \b Struct \b Name: HVD_BBU_Info 883 /// @brief \b Struct \b Description: Store the packet information 884 //----------------------------------------------------------------------------- 885 typedef struct 886 { 887 MS_U32 u32Staddr; ///< Packet offset from bitstream buffer base address. unit: byte. 888 MS_U32 u32Length; ///< Packet size. unit: byte. 889 MS_U32 u32Staddr2; ///< Packet offset from bitstream buffer base address. unit: byte. 890 MS_U32 u32Length2; ///< Packet size. unit: byte. 891 MS_U32 u32TimeStamp; ///< Packet time stamp. unit: ms. 892 MS_U32 u32ID_L; ///< Packet ID low part. 893 MS_U32 u32ID_H; ///< Packet ID high part. 894 MS_U32 u32AllocLength; ///< Allocated Packet size. unit: byte. 895 MS_U32 u32OriPktAddr; ///< Original packet offset from bitstream buffer base address. unit: byte. 896 MS_BOOL bRVBrokenPacket; ///< the RV only 897 } HVD_BBU_Info; 898 899 //----------------------------------------------------------------------------- 900 /// @brief \b Struct \b Name: HVD_Alive_Status 901 /// @brief \b Struct \b Description: Store the decoder living information 902 //----------------------------------------------------------------------------- 903 typedef struct 904 { 905 MS_U32 u32DecCnt; 906 MS_U32 u32SkipCnt; 907 MS_U32 u32IdleCnt; 908 MS_U32 u32MainLoopCnt; 909 } HVD_Alive_Status; 910 911 //----------------------------------------------------------------------------- 912 /// @brief \b Struct \b Name: HVD_DISP_INFO_THRESHOLD 913 /// @brief \b Struct \b Description: Store the disp information threshold. 914 //----------------------------------------------------------------------------- 915 typedef struct 916 { 917 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 918 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 919 MS_U32 u32MvopUpBound; //mvop filter upper bound 920 MS_U32 u32MvopLowBound; //mvop filter lower bound 921 } HVD_Disp_Info_TH; 922 923 //----------------------------------------------------------------------------- 924 /// @brief \b Struct \b Name: HVD_Settings 925 /// @brief \b Struct \b Description: Store the settings of user requirment 926 //----------------------------------------------------------------------------- 927 typedef struct 928 { 929 // TODO: currently only DTV settings. Need to add more settings for MM. 930 // Mode 931 HVD_Disp_Info_TH DispInfoTH; 932 MS_U32 u32IsrEvent; 933 MS_BOOL bEnISR; 934 935 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 936 MS_U8 bIsShowErrFrm; 937 MS_U8 u8FrcMode; //HVD_EX_FrmRateConvMode 938 939 MS_BOOL bIsErrConceal; 940 MS_BOOL bAutoFreeES; 941 MS_BOOL bDisDeblocking; 942 MS_BOOL bDisQuarterPixel; 943 944 MS_U8 bIsSyncOn; 945 MS_U32 u32SyncTolerance; 946 MS_U32 u32SyncRepeatTH; 947 MS_U32 u32SyncVideoDelay; 948 MS_U32 u32SyncFreeRunTH; 949 MS_U32 u32MiuBurstLevel; 950 } HVD_Settings; 951 952 //----------------------------------------------------------------------------- 953 /// @brief \b Struct \b Name: HVD_CC_Info 954 /// @brief \b Struct \b Description: HVD Close Caption Infomation. 955 //----------------------------------------------------------------------------- 956 typedef struct 957 { 958 MS_U8 u8UserDataMode; 959 MS_U8 u8ParsingStatus; 960 MS_BOOL b708Enable; 961 MS_BOOL b608InfoEnhance; 962 //MS_BOOL bBufMiu1[2]; 963 MS_U8 u8BufMiuSel[2]; 964 MS_BOOL bOverFlow[2]; 965 MS_U32 u32RingBufStartPAddr[2];//physical address 966 MS_U32 u32RingBufLen[2]; 967 MS_U32 volatile u32RingBufVacancy[2]; 968 MS_U32 volatile u32RingBufRPAddr[2], u32RingBufWPAddr[2];//physical address 969 MS_U32 volatile u32FWUsrDataRIdx, u32FWUsrDataWIdx; 970 MS_U32 u32PktLen708; 971 MS_U32 u32PktHdrAddr708; 972 MS_U8 u8CC608buf[512]; 973 MS_U8 u8CC708buf[512]; 974 } HVD_CC_Info; 975 976 typedef struct 977 { 978 MS_U16 u16TmpRef; 979 MS_U16 u16PicStruct; 980 MS_U32 u32Pts; 981 MS_U8 u8UsrDataCnt; 982 } HVD_CC_608EnhanceInfo; 983 984 985 //----------------------------------------------------------------------------- 986 /// @brief \b Struct \b Name: HVD_ISR_Ctrl 987 /// @brief \b Struct \b Description: HVD driver ISR control. 988 //----------------------------------------------------------------------------- 989 typedef struct 990 { 991 MS_BOOL bRegISR; 992 MS_BOOL bInISR; 993 MS_U32 u32ISRInfo; 994 MS_U32 u32IntCount; 995 HVD_ISRCallBack pfnISRCallBack; 996 MS_BOOL bDisableISRFlag; 997 MS_BOOL bIsHvdIsr; 998 MS_BOOL bIsG2Vp9Isr; 999 } HVD_ISR_Ctrl; 1000 1001 //----------------------------------------------------------------------------- 1002 /// @brief \b Struct \b Name: HVD_EX_Drv_Ctrl 1003 /// @brief \b Struct \b Description: HVD driver internal control. 1004 //----------------------------------------------------------------------------- 1005 typedef struct 1006 { 1007 // init stage 1008 MS_BOOL bUsed; 1009 HVD_EX_MemMap MemMap; ///< HVD memory config 1010 HVD_Init_Params InitParams; ///< HVD init settings 1011 MS_BOOL bNoDrvProccBuf; 1012 MS_BOOL bAutoRmLastZeroByte; 1013 MS_BOOL bCannotAccessMIU256; 1014 MS_U32 u32CmdTimeout; ///< HVD FW command timeout 1015 void *pLastFrmInfo; 1016 1017 // reset stage 1018 MS_U32 u32CtrlMode; ///< HVD run-time control flag 1019 MS_U32 u32DummyWriteBuf; ///< For dummy write MIU action. 1020 //MS_U32 u32CPUNonCacheMask; ///< CPU non-cache mask 1021 MS_U32 u32NULLPacketSize; ///< to store the size of AVI null packet pattern 1022 MS_U32 u32NULLPacketAddr; ///< to store the start address of AVI null packet pattern from bitstream buffer base. 1023 MS_U32 u32RV_FlushPacketSize; ///< to store the size of rm flush packet pattern 1024 MS_U32 u32RV_FlushPacketAddr; ///< to store the start address of rm flush packet pattern from bitstream buffer base. 1025 MS_U32 u32StepDecodeCnt; 1026 //MS_U32 u32LastBBUPTS; 1027 //MS_U32 u32DummyDataSize; ///< buffer size of dummy data. 1028 //MS_U32 u32RestSizeofPushDummy; 1029 //MS_U32 u32AddrPushDummy; 1030 MS_U32 u32LastESRptr; 1031 MS_U32 u32BBUTblInBitstreamBufAddr; 1032 MS_U32 u32BBUPacketCnt; 1033 MS_U32 u32BBUWptr_Fired; 1034 MS_U32 u32LastErrCode; 1035 //MS_BOOL bPushingDummy; 1036 MS_BOOL bIsDispInfoChg; 1037 MS_BOOL bFrmRateSupported; 1038 HVD_Nal_Entry LastNal; 1039 HVD_Alive_Status LivingStatus; 1040 1041 // recovery stage 1042 MS_BOOL bStepDecoding; 1043 HVD_Settings Settings; 1044 1045 MS_U8 bTurboFWMode; //TRUE:not reload FW more than once if pre-decoder is the same. 1046 1047 // ISR control 1048 HVD_ISR_Ctrl HVDISRCtrl; 1049 MS_U32 u32Sid; // stream ID 1050 1051 // user data 1052 MS_U32 u32UsrDataRd; 1053 MS_U32 u32UsrDataWr; 1054 HVD_CC_Info CloseCaptionInfo; 1055 1056 MS_U32 u32FlushRstPtr; ///< flush rst ptr: 0: init, 1:after flush and before push packet 1057 1058 // Secure Mode 1059 MS_U8 u8SecureMode; // Enum HVD_SECURE_MODE 1060 MS_U8 u8SettingMode; // Record Setting mode 1061 MS_U8 u8Resv[2]; 1062 MS_U32 u32ExternalDSbuf; // External DS buffer 1063 MS_U8 u8CodeMiuSel; 1064 MS_U8 u8ESMiuSel; 1065 MS_U8 u8FrmMiuSel; 1066 MS_U8 u8DrvProccMiuSel; 1067 } HVD_EX_Drv_Ctrl; 1068 1069 typedef void(*P_SC_ISR_Proc)(MS_U8 u8SCID); 1070 1071 1072 typedef struct 1073 { 1074 MS_BOOL bEnable; 1075 MS_U32 u32IapGnBufAddr; 1076 MS_U32 u32IapGnBufSize; 1077 } HVD_EX_IapGnBufShareBWMode; 1078 1079 1080 1081 typedef struct 1082 { 1083 MS_BOOL bOnePendingBuffer; 1084 MS_BOOL bFrameRateHandling; 1085 MS_U32 u32PreSetFrameRate; 1086 HVD_EX_IapGnBufShareBWMode stIapGnShBWMode; 1087 MS_BOOL bDisableTspInBbuMode; 1088 } HVD_Pre_Ctrl; 1089 1090 //------------------------------------------------------------------------------------------------- 1091 // Function and Variable 1092 //------------------------------------------------------------------------------------------------- 1093 extern MS_U32 u32UartCtrl; 1094 //extern MS_U32 u32InitSysTimeBase; 1095 1096 #endif // _DRV_HVD_DEF_H_ 1097 1098