1 /* 2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 3 * 4 * Based on: mach-davinci/emac_defs.h 5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _DAVINCI_EMAC_H_ 11 #define _DAVINCI_EMAC_H_ 12 /* Ethernet Min/Max packet size */ 13 #define EMAC_MIN_ETHERNET_PKT_SIZE 60 14 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518 15 /* Buffer size (should be aligned on 32 byte and cache line) */ 16 #define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ 17 ARCH_DMA_MINALIGN) 18 19 /* Number of RX packet buffers 20 * NOTE: Only 1 buffer supported as of now 21 */ 22 #define EMAC_MAX_RX_BUFFERS 10 23 24 25 /*********************************************** 26 ******** Internally used macros *************** 27 ***********************************************/ 28 29 #define EMAC_CH_TX 1 30 #define EMAC_CH_RX 0 31 32 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and 33 * reserve space for 64 descriptors max 34 */ 35 #define EMAC_RX_DESC_BASE 0x0 36 #define EMAC_TX_DESC_BASE 0x1000 37 38 /* EMAC Teardown value */ 39 #define EMAC_TEARDOWN_VALUE 0xfffffffc 40 41 /* MII Status Register */ 42 #define MII_STATUS_REG 1 43 /* PHY Configuration register */ 44 #define PHY_CONF_TXCLKEN (1 << 5) 45 46 /* Number of statistics registers */ 47 #define EMAC_NUM_STATS 36 48 49 50 /* EMAC Descriptor */ 51 typedef volatile struct _emac_desc 52 { 53 u_int32_t next; /* Pointer to next descriptor 54 in chain */ 55 u_int8_t *buffer; /* Pointer to data buffer */ 56 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ 57 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ 58 } emac_desc; 59 60 /* CPPI bit positions */ 61 #define EMAC_CPPI_SOP_BIT (0x80000000) 62 #define EMAC_CPPI_EOP_BIT (0x40000000) 63 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) 64 #define EMAC_CPPI_EOQ_BIT (0x10000000) 65 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) 66 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000) 67 68 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) 69 70 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) 71 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) 72 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) 73 #define EMAC_MACCONTROL_GIGFORCE (1 << 17) 74 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) 75 76 #define EMAC_MAC_ADDR_MATCH (1 << 19) 77 #define EMAC_MAC_ADDR_IS_VALID (1 << 20) 78 79 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) 80 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) 81 82 83 #define MDIO_CONTROL_IDLE (0x80000000) 84 #define MDIO_CONTROL_ENABLE (0x40000000) 85 #define MDIO_CONTROL_FAULT_ENABLE (0x40000) 86 #define MDIO_CONTROL_FAULT (0x80000) 87 #define MDIO_USERACCESS0_GO (0x80000000) 88 #define MDIO_USERACCESS0_WRITE_READ (0x0) 89 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) 90 #define MDIO_USERACCESS0_ACK (0x20000000) 91 92 /* Ethernet MAC Registers Structure */ 93 typedef struct { 94 dv_reg TXIDVER; 95 dv_reg TXCONTROL; 96 dv_reg TXTEARDOWN; 97 u_int8_t RSVD0[4]; 98 dv_reg RXIDVER; 99 dv_reg RXCONTROL; 100 dv_reg RXTEARDOWN; 101 u_int8_t RSVD1[100]; 102 dv_reg TXINTSTATRAW; 103 dv_reg TXINTSTATMASKED; 104 dv_reg TXINTMASKSET; 105 dv_reg TXINTMASKCLEAR; 106 dv_reg MACINVECTOR; 107 u_int8_t RSVD2[12]; 108 dv_reg RXINTSTATRAW; 109 dv_reg RXINTSTATMASKED; 110 dv_reg RXINTMASKSET; 111 dv_reg RXINTMASKCLEAR; 112 dv_reg MACINTSTATRAW; 113 dv_reg MACINTSTATMASKED; 114 dv_reg MACINTMASKSET; 115 dv_reg MACINTMASKCLEAR; 116 u_int8_t RSVD3[64]; 117 dv_reg RXMBPENABLE; 118 dv_reg RXUNICASTSET; 119 dv_reg RXUNICASTCLEAR; 120 dv_reg RXMAXLEN; 121 dv_reg RXBUFFEROFFSET; 122 dv_reg RXFILTERLOWTHRESH; 123 u_int8_t RSVD4[8]; 124 dv_reg RX0FLOWTHRESH; 125 dv_reg RX1FLOWTHRESH; 126 dv_reg RX2FLOWTHRESH; 127 dv_reg RX3FLOWTHRESH; 128 dv_reg RX4FLOWTHRESH; 129 dv_reg RX5FLOWTHRESH; 130 dv_reg RX6FLOWTHRESH; 131 dv_reg RX7FLOWTHRESH; 132 dv_reg RX0FREEBUFFER; 133 dv_reg RX1FREEBUFFER; 134 dv_reg RX2FREEBUFFER; 135 dv_reg RX3FREEBUFFER; 136 dv_reg RX4FREEBUFFER; 137 dv_reg RX5FREEBUFFER; 138 dv_reg RX6FREEBUFFER; 139 dv_reg RX7FREEBUFFER; 140 dv_reg MACCONTROL; 141 dv_reg MACSTATUS; 142 dv_reg EMCONTROL; 143 dv_reg FIFOCONTROL; 144 dv_reg MACCONFIG; 145 dv_reg SOFTRESET; 146 u_int8_t RSVD5[88]; 147 dv_reg MACSRCADDRLO; 148 dv_reg MACSRCADDRHI; 149 dv_reg MACHASH1; 150 dv_reg MACHASH2; 151 dv_reg BOFFTEST; 152 dv_reg TPACETEST; 153 dv_reg RXPAUSE; 154 dv_reg TXPAUSE; 155 u_int8_t RSVD6[16]; 156 dv_reg RXGOODFRAMES; 157 dv_reg RXBCASTFRAMES; 158 dv_reg RXMCASTFRAMES; 159 dv_reg RXPAUSEFRAMES; 160 dv_reg RXCRCERRORS; 161 dv_reg RXALIGNCODEERRORS; 162 dv_reg RXOVERSIZED; 163 dv_reg RXJABBER; 164 dv_reg RXUNDERSIZED; 165 dv_reg RXFRAGMENTS; 166 dv_reg RXFILTERED; 167 dv_reg RXQOSFILTERED; 168 dv_reg RXOCTETS; 169 dv_reg TXGOODFRAMES; 170 dv_reg TXBCASTFRAMES; 171 dv_reg TXMCASTFRAMES; 172 dv_reg TXPAUSEFRAMES; 173 dv_reg TXDEFERRED; 174 dv_reg TXCOLLISION; 175 dv_reg TXSINGLECOLL; 176 dv_reg TXMULTICOLL; 177 dv_reg TXEXCESSIVECOLL; 178 dv_reg TXLATECOLL; 179 dv_reg TXUNDERRUN; 180 dv_reg TXCARRIERSENSE; 181 dv_reg TXOCTETS; 182 dv_reg FRAME64; 183 dv_reg FRAME65T127; 184 dv_reg FRAME128T255; 185 dv_reg FRAME256T511; 186 dv_reg FRAME512T1023; 187 dv_reg FRAME1024TUP; 188 dv_reg NETOCTETS; 189 dv_reg RXSOFOVERRUNS; 190 dv_reg RXMOFOVERRUNS; 191 dv_reg RXDMAOVERRUNS; 192 u_int8_t RSVD7[624]; 193 dv_reg MACADDRLO; 194 dv_reg MACADDRHI; 195 dv_reg MACINDEX; 196 u_int8_t RSVD8[244]; 197 dv_reg TX0HDP; 198 dv_reg TX1HDP; 199 dv_reg TX2HDP; 200 dv_reg TX3HDP; 201 dv_reg TX4HDP; 202 dv_reg TX5HDP; 203 dv_reg TX6HDP; 204 dv_reg TX7HDP; 205 dv_reg RX0HDP; 206 dv_reg RX1HDP; 207 dv_reg RX2HDP; 208 dv_reg RX3HDP; 209 dv_reg RX4HDP; 210 dv_reg RX5HDP; 211 dv_reg RX6HDP; 212 dv_reg RX7HDP; 213 dv_reg TX0CP; 214 dv_reg TX1CP; 215 dv_reg TX2CP; 216 dv_reg TX3CP; 217 dv_reg TX4CP; 218 dv_reg TX5CP; 219 dv_reg TX6CP; 220 dv_reg TX7CP; 221 dv_reg RX0CP; 222 dv_reg RX1CP; 223 dv_reg RX2CP; 224 dv_reg RX3CP; 225 dv_reg RX4CP; 226 dv_reg RX5CP; 227 dv_reg RX6CP; 228 dv_reg RX7CP; 229 } emac_regs; 230 231 /* EMAC Wrapper Registers Structure */ 232 typedef struct { 233 #ifdef DAVINCI_EMAC_VERSION2 234 dv_reg idver; 235 dv_reg softrst; 236 dv_reg emctrl; 237 dv_reg c0rxthreshen; 238 dv_reg c0rxen; 239 dv_reg c0txen; 240 dv_reg c0miscen; 241 dv_reg c1rxthreshen; 242 dv_reg c1rxen; 243 dv_reg c1txen; 244 dv_reg c1miscen; 245 dv_reg c2rxthreshen; 246 dv_reg c2rxen; 247 dv_reg c2txen; 248 dv_reg c2miscen; 249 dv_reg c0rxthreshstat; 250 dv_reg c0rxstat; 251 dv_reg c0txstat; 252 dv_reg c0miscstat; 253 dv_reg c1rxthreshstat; 254 dv_reg c1rxstat; 255 dv_reg c1txstat; 256 dv_reg c1miscstat; 257 dv_reg c2rxthreshstat; 258 dv_reg c2rxstat; 259 dv_reg c2txstat; 260 dv_reg c2miscstat; 261 dv_reg c0rximax; 262 dv_reg c0tximax; 263 dv_reg c1rximax; 264 dv_reg c1tximax; 265 dv_reg c2rximax; 266 dv_reg c2tximax; 267 #else 268 u_int8_t RSVD0[4100]; 269 dv_reg EWCTL; 270 dv_reg EWINTTCNT; 271 #endif 272 } ewrap_regs; 273 274 /* EMAC MDIO Registers Structure */ 275 typedef struct { 276 dv_reg VERSION; 277 dv_reg CONTROL; 278 dv_reg ALIVE; 279 dv_reg LINK; 280 dv_reg LINKINTRAW; 281 dv_reg LINKINTMASKED; 282 u_int8_t RSVD0[8]; 283 dv_reg USERINTRAW; 284 dv_reg USERINTMASKED; 285 dv_reg USERINTMASKSET; 286 dv_reg USERINTMASKCLEAR; 287 u_int8_t RSVD1[80]; 288 dv_reg USERACCESS0; 289 dv_reg USERPHYSEL0; 290 dv_reg USERACCESS1; 291 dv_reg USERPHYSEL1; 292 } mdio_regs; 293 294 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data); 295 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data); 296 297 typedef struct { 298 char name[64]; 299 int (*init)(int phy_addr); 300 int (*is_phy_connected)(int phy_addr); 301 int (*get_link_speed)(int phy_addr); 302 int (*auto_negotiate)(int phy_addr); 303 } phy_t; 304 305 #endif /* _DAVINCI_EMAC_H_ */ 306