1 /*
2 * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <drivers/delay_timer.h>
11 #include <drivers/scmi.h>
12 #include <lib/mmio.h>
13 #include <platform_def.h>
14
15 #include <plat_private.h>
16 #include "rk3588_clk.h"
17 #include <rockchip_sip_svc.h>
18 #include <scmi_clock.h>
19 #include <soc.h>
20
21 enum pll_type_sel {
22 PLL_SEL_AUTO, /* all plls (normal pll or pvtpll) */
23 PLL_SEL_PVT,
24 PLL_SEL_NOR,
25 PLL_SEL_AUTO_NOR /* all normal plls (apll/gpll/npll) */
26 };
27
28 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
29
30 #define RK3588_CPUL_PVTPLL_CON0_L 0x40
31 #define RK3588_CPUL_PVTPLL_CON0_H 0x44
32 #define RK3588_CPUL_PVTPLL_CON1 0x48
33 #define RK3588_CPUL_PVTPLL_CON2 0x4c
34 #define RK3588_CPUL_PVTPLL_STATUS 0x60
35 #define RK3588_CPUB_PVTPLL_CON0_L 0x00
36 #define RK3588_CPUB_PVTPLL_CON0_H 0x04
37 #define RK3588_CPUB_PVTPLL_CON1 0x08
38 #define RK3588_CPUB_PVTPLL_CON2 0x0c
39 #define RK3588_CPUB_PVTPLL_STATUS 0x18
40 #define RK3588_DSU_PVTPLL_CON0_L 0x60
41 #define RK3588_DSU_PVTPLL_CON0_H 0x64
42 #define RK3588_DSU_PVTPLL_CON1 0x70
43 #define RK3588_DSU_PVTPLL_CON2 0x74
44 #define RK3588_DSU_PVTPLL_STATUS 0x80
45 #define RK3588_GPU_PVTPLL_CON0_L 0x00
46 #define RK3588_GPU_PVTPLL_CON0_H 0x04
47 #define RK3588_GPU_PVTPLL_CON1 0x08
48 #define RK3588_GPU_PVTPLL_CON2 0x0c
49 #define RK3588_GPU_PVTPLL_STATUS 0x18
50 #define RK3588_NPU_PVTPLL_CON0_L 0x0c
51 #define RK3588_NPU_PVTPLL_CON0_H 0x10
52 #define RK3588_NPU_PVTPLL_CON1 0x14
53 #define RK3588_NPU_PVTPLL_CON2 0x18
54 #define RK3588_NPU_PVTPLL_STATUS 0x24
55 #define RK3588_PVTPLL_MAX_LENGTH 0x3f
56
57 #define GPLL_RATE 1188000000
58 #define CPLL_RATE 1500000000
59 #define SPLL_RATE 702000000
60 #define AUPLL_RATE 786431952
61 #define NPLL_RATE 850000000
62
63 #define MAX_RATE_TABLE 16
64
65 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift)
66 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift)
67 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift)
68 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift)
69 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift)
70 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift)
71
72 #define CPU_PLL_PATH_SLOWMODE BITS_WITH_WMASK(0U, 0x3U, 0)
73 #define CPU_PLL_PATH_NORMAL BITS_WITH_WMASK(1U, 0x3U, 0)
74 #define CPU_PLL_PATH_DEEP_SLOW BITS_WITH_WMASK(2U, 0x3U, 0)
75
76 #define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13)
77 #define CRU_PLL_POWER_UP WMSK_BIT(13)
78
79 /* core_i: from gpll or apll */
80 #define CLK_CORE_I_SEL_APLL WMSK_BIT(6)
81 #define CLK_CORE_I_SEL_GPLL BIT_WITH_WMSK(6)
82
83 /* clk_core:
84 * from normal pll(core_i: gpll or apll) path or direct pass from apll
85 */
86
87 /* cpul clk path */
88 #define CPUL_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 14)
89 #define CPUL_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 14)
90 #define CPUL_CLK_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 14)
91
92 #define CPUL_CLK_PATH_LPLL (BITS_WITH_WMASK(0U, 0x3U, 5) | \
93 BITS_WITH_WMASK(0U, 0x3U, 12))
94 #define CPUL_CLK_PATH_DIR_LPLL (BITS_WITH_WMASK(0x1, 0x3U, 5) | \
95 BITS_WITH_WMASK(1U, 0x3U, 12))
96 #define CPUL_CLK_PATH_PVTPLL (BITS_WITH_WMASK(0x2, 0x3U, 5) | \
97 BITS_WITH_WMASK(2U, 0x3U, 12))
98
99 #define CPUL_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 14)
100 #define CPUL_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 14)
101
102 /* cpub01 clk path */
103 #define CPUB01_CLK_PATH_NOR_XIN BITS_WITH_WMASK(0U, 0x3U, 6)
104 #define CPUB01_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(1U, 0x3U, 6)
105 #define CPUB01_CLK_PATH_NOR_B0PLL BITS_WITH_WMASK(2U, 0x3U, 6)
106
107 #define CPUB01_CLK_PATH_B0PLL BITS_WITH_WMASK(0U, 0x3U, 13)
108 #define CPUB01_CLK_PATH_DIR_B0PLL BITS_WITH_WMASK(1U, 0x3U, 13)
109 #define CPUB01_CLK_PATH_B0_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 13)
110
111 #define CPUB01_CLK_PATH_B1PLL BITS_WITH_WMASK(0U, 0x3U, 5)
112 #define CPUB01_CLK_PATH_DIR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 5)
113 #define CPUB01_CLK_PATH_B1_PVTPLL BITS_WITH_WMASK(2U, 0x3U, 5)
114
115 #define CPUB01_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 2)
116 #define CPUB01_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 2)
117
118 #define CPUB_PCLK_PATH_100M BITS_WITH_WMASK(0U, 0x3U, 0)
119 #define CPUB_PCLK_PATH_50M BITS_WITH_WMASK(1U, 0x3U, 0)
120 #define CPUB_PCLK_PATH_24M BITS_WITH_WMASK(2U, 0x3U, 0)
121
122 /* dsu clk path */
123 #define SCLK_DSU_PATH_NOR_B0PLL BITS_WITH_WMASK(0U, 0x3U, 12)
124 #define SCLK_DSU_PATH_NOR_B1PLL BITS_WITH_WMASK(1U, 0x3U, 12)
125 #define SCLK_DSU_PATH_NOR_LPLL BITS_WITH_WMASK(2U, 0x3U, 12)
126 #define SCLK_DSU_PATH_NOR_GPLL BITS_WITH_WMASK(3U, 0x3U, 12)
127
128 #define DSU_PVTPLL_PATH_DEEP_SLOW BITS_WITH_WMASK(0U, 0x1U, 15)
129 #define DSU_PVTPLL_PATH_PVTPLL BITS_WITH_WMASK(1U, 0x1U, 15)
130
131 #define SCLK_DSU_PATH_NOR_PLL WMSK_BIT(0)
132 #define SCLK_DSU_PATH_PVTPLL BIT_WITH_WMSK(0)
133
134 /* npu clk path */
135 #define NPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 7)
136 #define NPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 7)
137 #define NPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 7)
138 #define NPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 7)
139 #define NPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 7)
140
141 #define NPU_CLK_PATH_NOR_PLL WMSK_BIT(0)
142 #define NPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(0)
143
144 /* gpu clk path */
145 #define GPU_CLK_PATH_NOR_GPLL BITS_WITH_WMASK(0U, 0x7U, 5)
146 #define GPU_CLK_PATH_NOR_CPLL BITS_WITH_WMASK(1U, 0x7U, 5)
147 #define GPU_CLK_PATH_NOR_AUPLL BITS_WITH_WMASK(2U, 0x7U, 5)
148 #define GPU_CLK_PATH_NOR_NPLL BITS_WITH_WMASK(3U, 0x7U, 5)
149 #define GPU_CLK_PATH_NOR_SPLL BITS_WITH_WMASK(4U, 0x7U, 5)
150 #define GPU_CLK_PATH_NOR_PLL WMSK_BIT(14)
151 #define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(14)
152
153 #define PVTPLL_NEED(type, length) (((type) == PLL_SEL_PVT || \
154 (type) == PLL_SEL_AUTO) && \
155 (length))
156
157 struct pvtpll_table {
158 unsigned int rate;
159 uint32_t length;
160 uint32_t ring_sel;
161 };
162
163 struct sys_clk_info_t {
164 struct pvtpll_table *cpul_table;
165 struct pvtpll_table *cpub01_table;
166 struct pvtpll_table *cpub23_table;
167 struct pvtpll_table *gpu_table;
168 struct pvtpll_table *npu_table;
169 unsigned int cpul_rate_count;
170 unsigned int cpub01_rate_count;
171 unsigned int cpub23_rate_count;
172 unsigned int gpu_rate_count;
173 unsigned int npu_rate_count;
174 unsigned long cpul_rate;
175 unsigned long dsu_rate;
176 unsigned long cpub01_rate;
177 unsigned long cpub23_rate;
178 unsigned long gpu_rate;
179 unsigned long npu_rate;
180 };
181
182 #define RK3588_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \
183 { \
184 .id = _id, \
185 .name = _name, \
186 .clk_ops = _data, \
187 .rate_table = _table, \
188 .rate_cnt = _cnt, \
189 .is_security = _is_s, \
190 }
191
192 #define ROCKCHIP_PVTPLL(_rate, _sel, _len) \
193 { \
194 .rate = _rate##U, \
195 .ring_sel = _sel, \
196 .length = _len, \
197 }
198
199 static struct pvtpll_table rk3588_cpul_pvtpll_table[] = {
200 /* rate_hz, ring_sel, length */
201 ROCKCHIP_PVTPLL(1800000000, 1, 15),
202 ROCKCHIP_PVTPLL(1704000000, 1, 15),
203 ROCKCHIP_PVTPLL(1608000000, 1, 15),
204 ROCKCHIP_PVTPLL(1416000000, 1, 15),
205 ROCKCHIP_PVTPLL(1200000000, 1, 17),
206 ROCKCHIP_PVTPLL(1008000000, 1, 22),
207 ROCKCHIP_PVTPLL(816000000, 1, 32),
208 ROCKCHIP_PVTPLL(600000000, 0, 0),
209 ROCKCHIP_PVTPLL(408000000, 0, 0),
210 { /* sentinel */ },
211 };
212
213 static struct pvtpll_table rk3588_cpub0_pvtpll_table[] = {
214 /* rate_hz, ring_sel, length */
215 ROCKCHIP_PVTPLL(2400000000, 1, 11),
216 ROCKCHIP_PVTPLL(2352000000, 1, 11),
217 ROCKCHIP_PVTPLL(2304000000, 1, 11),
218 ROCKCHIP_PVTPLL(2256000000, 1, 11),
219 ROCKCHIP_PVTPLL(2208000000, 1, 11),
220 ROCKCHIP_PVTPLL(2112000000, 1, 11),
221 ROCKCHIP_PVTPLL(2016000000, 1, 11),
222 ROCKCHIP_PVTPLL(1800000000, 1, 11),
223 ROCKCHIP_PVTPLL(1608000000, 1, 11),
224 ROCKCHIP_PVTPLL(1416000000, 1, 13),
225 ROCKCHIP_PVTPLL(1200000000, 1, 17),
226 ROCKCHIP_PVTPLL(1008000000, 1, 23),
227 ROCKCHIP_PVTPLL(816000000, 1, 33),
228 ROCKCHIP_PVTPLL(600000000, 0, 0),
229 ROCKCHIP_PVTPLL(408000000, 0, 0),
230 { /* sentinel */ },
231 };
232
233 static struct
234 pvtpll_table rk3588_cpub1_pvtpll_table[ARRAY_SIZE(rk3588_cpub0_pvtpll_table)] = { 0 };
235
236 static struct pvtpll_table rk3588_gpu_pvtpll_table[] = {
237 /* rate_hz, ring_sel, length */
238 ROCKCHIP_PVTPLL(1000000000, 1, 12),
239 ROCKCHIP_PVTPLL(900000000, 1, 12),
240 ROCKCHIP_PVTPLL(800000000, 1, 12),
241 ROCKCHIP_PVTPLL(700000000, 1, 13),
242 ROCKCHIP_PVTPLL(600000000, 1, 17),
243 ROCKCHIP_PVTPLL(500000000, 1, 25),
244 ROCKCHIP_PVTPLL(400000000, 1, 38),
245 ROCKCHIP_PVTPLL(300000000, 1, 55),
246 ROCKCHIP_PVTPLL(200000000, 0, 0),
247 { /* sentinel */ },
248 };
249
250 static struct pvtpll_table rk3588_npu_pvtpll_table[] = {
251 /* rate_hz, ring_sel, length */
252 ROCKCHIP_PVTPLL(1000000000, 1, 12),
253 ROCKCHIP_PVTPLL(900000000, 1, 12),
254 ROCKCHIP_PVTPLL(800000000, 1, 12),
255 ROCKCHIP_PVTPLL(700000000, 1, 13),
256 ROCKCHIP_PVTPLL(600000000, 1, 17),
257 ROCKCHIP_PVTPLL(500000000, 1, 25),
258 ROCKCHIP_PVTPLL(400000000, 1, 38),
259 ROCKCHIP_PVTPLL(300000000, 1, 55),
260 ROCKCHIP_PVTPLL(200000000, 0, 0),
261 { /* sentinel */ },
262 };
263
264 static unsigned long rk3588_cpul_rates[] = {
265 408000000, 600000000, 816000000, 1008000000,
266 1200000000, 1416000000, 1608000000, 1800000063,
267 };
268
269 static unsigned long rk3588_cpub_rates[] = {
270 408000000, 816000000, 1008000000, 1200000000,
271 1416000000, 1608000000, 1800000000, 2016000000,
272 2208000000, 2304000000, 2400000063
273 };
274
275 static unsigned long rk3588_gpu_rates[] = {
276 200000000, 300000000, 400000000, 500000000,
277 600000000, 700000000, 800000000, 900000000,
278 1000000063
279 };
280
281 static unsigned long rk3588_sbus_rates[] = {
282 24000000, 50000000, 100000000, 150000000, 200000000,
283 250000000, 350000000, 700000000
284 };
285
286 static unsigned long rk3588_sdmmc_rates[] = {
287 400000, 24000000, 50000000, 100000000, 150000000, 200000000,
288 300000000, 400000000, 600000000, 700000000
289 };
290
291 static struct sys_clk_info_t sys_clk_info;
292 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
293
rkclk_get_pvtpll_config(struct pvtpll_table * table,unsigned int count,unsigned int freq_hz)294 static struct pvtpll_table *rkclk_get_pvtpll_config(struct pvtpll_table *table,
295 unsigned int count,
296 unsigned int freq_hz)
297 {
298 int i;
299
300 for (i = 0; i < count; i++) {
301 if (freq_hz == table[i].rate)
302 return &table[i];
303 }
304 return NULL;
305 }
306
clk_cpul_set_rate(unsigned long rate,enum pll_type_sel type)307 static int clk_cpul_set_rate(unsigned long rate, enum pll_type_sel type)
308 {
309 struct pvtpll_table *pvtpll;
310 int div;
311
312 if (rate == 0)
313 return SCMI_INVALID_PARAMETERS;
314
315 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table,
316 sys_clk_info.cpul_rate_count, rate);
317 if (pvtpll == NULL)
318 return SCMI_INVALID_PARAMETERS;
319
320 /* set lpll */
321 if (PVTPLL_NEED(type, pvtpll->length) != 0) {
322 /* set clock gating interval */
323 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON2,
324 0x00040000);
325 /* set ring sel */
326 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L,
327 0x07000000 | (pvtpll->ring_sel << 8));
328 /* set length */
329 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_H,
330 0x003f0000 | pvtpll->length);
331 /* set cal cnt = 24, T = 1us */
332 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON1,
333 0x18);
334 /* enable pvtpll */
335 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L,
336 0x00020002);
337 /* start monitor */
338 mmio_write_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_CON0_L,
339 0x00010001);
340 /* set corel mux pvtpll */
341 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),
342 CPUL_PVTPLL_PATH_PVTPLL);
343 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),
344 CPUL_CLK_PATH_PVTPLL);
345 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),
346 CPUL_CLK_PATH_PVTPLL);
347 return 0;
348 }
349
350 /* set clk corel div */
351 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;
352 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),
353 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7));
354 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),
355 CLKDIV_5BITS_SHF(div, 0) | CLKDIV_5BITS_SHF(div, 7));
356 /* set corel mux gpll */
357 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5),
358 CPUL_CLK_PATH_NOR_GPLL);
359 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(6),
360 CPUL_CLK_PATH_LPLL);
361 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),
362 CPUL_CLK_PATH_LPLL);
363
364 return 0;
365 }
366
clk_scmi_cpul_set_rate(rk_scmi_clock_t * clock,unsigned long rate)367 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
368 {
369 int ret;
370
371 if (rate == 0)
372 return SCMI_INVALID_PARAMETERS;
373
374 ret = clk_cpul_set_rate(rate, PLL_SEL_AUTO);
375 if (ret == 0) {
376 sys_clk_info.cpul_rate = rate;
377 ret = clk_scmi_dsu_set_rate(clock, rate);
378 }
379
380 return ret;
381 }
382
rk3588_lpll_get_rate(void)383 static unsigned long rk3588_lpll_get_rate(void)
384 {
385 unsigned int m, p, s, k;
386 uint64_t rate64 = 24000000, postdiv;
387 int mode;
388
389 mode = (mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) >> 14) &
390 0x3;
391
392 if (mode == 0)
393 return rate64;
394
395 m = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(16)) >>
396 CRU_PLLCON0_M_SHIFT) &
397 CRU_PLLCON0_M_MASK;
398 p = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >>
399 CRU_PLLCON1_P_SHIFT) &
400 CRU_PLLCON1_P_MASK;
401 s = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(17)) >>
402 CRU_PLLCON1_S_SHIFT) &
403 CRU_PLLCON1_S_MASK;
404 k = (mmio_read_32(DSUCRU_BASE + CRU_PLL_CON(18)) >>
405 CRU_PLLCON2_K_SHIFT) &
406 CRU_PLLCON2_K_MASK;
407
408 rate64 *= m;
409 rate64 = rate64 / p;
410
411 if (k != 0) {
412 /* fractional mode */
413 uint64_t frac_rate64 = 24000000 * k;
414
415 postdiv = p * 65535;
416 frac_rate64 = frac_rate64 / postdiv;
417 rate64 += frac_rate64;
418 }
419 rate64 = rate64 >> s;
420
421 return (unsigned long)rate64;
422 }
423
clk_scmi_cpul_get_rate(rk_scmi_clock_t * clock)424 static unsigned long clk_scmi_cpul_get_rate(rk_scmi_clock_t *clock)
425 {
426 int src, div;
427
428 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x0060;
429 src = src >> 5;
430 if (src == 2) {
431 udelay(2);
432 return (mmio_read_32(LITCOREGRF_BASE + RK3588_CPUL_PVTPLL_STATUS) & 0x3FFF) * MHz;
433 } else {
434 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(5)) & 0xc000;
435 src = src >> 14;
436 div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(6)) & 0x1f;
437 switch (src) {
438 case 0:
439 return 24000000;
440 case 1:
441 /* Make the return rate is equal to the set rate */
442 if (sys_clk_info.cpul_rate)
443 return sys_clk_info.cpul_rate;
444 else
445 return GPLL_RATE / (div + 1);
446 case 2:
447 return rk3588_lpll_get_rate();
448 default:
449 return 0;
450 }
451 }
452 }
453
clk_scmi_cpul_set_status(rk_scmi_clock_t * clock,bool status)454 static int clk_scmi_cpul_set_status(rk_scmi_clock_t *clock, bool status)
455 {
456 return 0;
457 }
458
clk_scmi_b0pll_disable(void)459 static void clk_scmi_b0pll_disable(void)
460 {
461 static bool is_b0pll_disabled;
462
463 if (is_b0pll_disabled != 0)
464 return;
465
466 /* set coreb01 mux gpll */
467 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
468 CPUB01_CLK_PATH_NOR_GPLL);
469 /* pll enter slow mode */
470 mmio_write_32(BIGCORE0CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE);
471 /* set pll power down */
472 mmio_write_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1), CRU_PLL_POWER_DOWN);
473
474 is_b0pll_disabled = true;
475 }
476
clk_cpub01_set_rate(unsigned long rate,enum pll_type_sel type)477 static int clk_cpub01_set_rate(unsigned long rate, enum pll_type_sel type)
478 {
479 struct pvtpll_table *pvtpll;
480 int div;
481
482 if (rate == 0)
483 return SCMI_INVALID_PARAMETERS;
484
485 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub01_table,
486 sys_clk_info.cpub01_rate_count, rate);
487 if (pvtpll == NULL)
488 return SCMI_INVALID_PARAMETERS;
489
490 /* set b0pll */
491 if (PVTPLL_NEED(type, pvtpll->length)) {
492 /* set clock gating interval */
493 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON2,
494 0x00040000);
495 /* set ring sel */
496 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
497 0x07000000 | (pvtpll->ring_sel << 8));
498 /* set length */
499 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H,
500 0x003f0000 | pvtpll->length);
501 /* set cal cnt = 24, T = 1us */
502 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON1,
503 0x18);
504 /* enable pvtpll */
505 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
506 0x00020002);
507 /* start monitor */
508 mmio_write_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
509 0x00010001);
510 /* set core mux pvtpll */
511 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2),
512 CPUB01_PVTPLL_PATH_PVTPLL);
513 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
514 CPUB01_CLK_PATH_B0_PVTPLL);
515 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1),
516 CPUB01_CLK_PATH_B1_PVTPLL);
517 goto out;
518 }
519
520 /* set clk coreb01 div */
521 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;
522 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
523 CLKDIV_5BITS_SHF(div, 8));
524 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1),
525 CLKDIV_5BITS_SHF(div, 0));
526 /* set coreb01 mux gpll */
527 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
528 CPUB01_CLK_PATH_NOR_GPLL);
529 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
530 CPUB01_CLK_PATH_B0PLL);
531 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(1),
532 CPUB01_CLK_PATH_B1PLL);
533
534 out:
535 clk_scmi_b0pll_disable();
536
537 return 0;
538 }
539
clk_scmi_cpub01_set_rate(rk_scmi_clock_t * clock,unsigned long rate)540 static int clk_scmi_cpub01_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
541 {
542 int ret;
543
544 if (rate == 0)
545 return SCMI_INVALID_PARAMETERS;
546
547 ret = clk_cpub01_set_rate(rate, PLL_SEL_AUTO);
548 if (ret == 0)
549 sys_clk_info.cpub01_rate = rate;
550
551 return ret;
552 }
553
rk3588_b0pll_get_rate(void)554 static unsigned long rk3588_b0pll_get_rate(void)
555 {
556 unsigned int m, p, s, k;
557 uint64_t rate64 = 24000000, postdiv;
558 int mode;
559
560 mode = (mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) &
561 0x3;
562
563 if (mode == 0)
564 return rate64;
565
566 m = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(0)) >>
567 CRU_PLLCON0_M_SHIFT) &
568 CRU_PLLCON0_M_MASK;
569 p = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >>
570 CRU_PLLCON1_P_SHIFT) &
571 CRU_PLLCON1_P_MASK;
572 s = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(1)) >>
573 CRU_PLLCON1_S_SHIFT) &
574 CRU_PLLCON1_S_MASK;
575 k = (mmio_read_32(BIGCORE0CRU_BASE + CRU_PLL_CON(2)) >>
576 CRU_PLLCON2_K_SHIFT) &
577 CRU_PLLCON2_K_MASK;
578
579 rate64 *= m;
580 rate64 = rate64 / p;
581
582 if (k != 0) {
583 /* fractional mode */
584 uint64_t frac_rate64 = 24000000 * k;
585
586 postdiv = p * 65535;
587 frac_rate64 = frac_rate64 / postdiv;
588 rate64 += frac_rate64;
589 }
590 rate64 = rate64 >> s;
591
592 return (unsigned long)rate64;
593 }
594
clk_scmi_cpub01_get_rate(rk_scmi_clock_t * clock)595 static unsigned long clk_scmi_cpub01_get_rate(rk_scmi_clock_t *clock)
596 {
597 int value, src, div;
598
599 value = mmio_read_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0));
600 src = (value & 0x6000) >> 13;
601 if (src == 2) {
602 udelay(2);
603 return (mmio_read_32(BIGCORE0GRF_BASE + RK3588_CPUB_PVTPLL_STATUS) & 0x3FFF) * MHz;
604 } else {
605 src = (value & 0x00c0) >> 6;
606 div = (value & 0x1f00) >> 8;
607 switch (src) {
608 case 0:
609 return 24000000;
610 case 1:
611 /* Make the return rate is equal to the set rate */
612 if (sys_clk_info.cpub01_rate)
613 return sys_clk_info.cpub01_rate;
614 else
615 return GPLL_RATE / (div + 1);
616 case 2:
617 return rk3588_b0pll_get_rate();
618 default:
619 return 0;
620 }
621 }
622 }
623
clk_scmi_cpub01_set_status(rk_scmi_clock_t * clock,bool status)624 static int clk_scmi_cpub01_set_status(rk_scmi_clock_t *clock, bool status)
625 {
626 return 0;
627 }
628
clk_scmi_b1pll_disable(void)629 static void clk_scmi_b1pll_disable(void)
630 {
631 static bool is_b1pll_disabled;
632
633 if (is_b1pll_disabled != 0)
634 return;
635
636 /* set coreb23 mux gpll */
637 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
638 CPUB01_CLK_PATH_NOR_GPLL);
639 /* pll enter slow mode */
640 mmio_write_32(BIGCORE1CRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE);
641 /* set pll power down */
642 mmio_write_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9), CRU_PLL_POWER_DOWN);
643
644 is_b1pll_disabled = true;
645 }
646
clk_cpub23_set_rate(unsigned long rate,enum pll_type_sel type)647 static int clk_cpub23_set_rate(unsigned long rate, enum pll_type_sel type)
648 {
649 struct pvtpll_table *pvtpll;
650 int div;
651
652 if (rate == 0)
653 return SCMI_INVALID_PARAMETERS;
654
655 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpub23_table,
656 sys_clk_info.cpub23_rate_count, rate);
657 if (pvtpll == NULL)
658 return SCMI_INVALID_PARAMETERS;
659
660 /* set b1pll */
661 if (PVTPLL_NEED(type, pvtpll->length)) {
662 /* set clock gating interval */
663 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON2,
664 0x00040000);
665 /* set ring sel */
666 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
667 0x07000000 | (pvtpll->ring_sel << 8));
668 /* set length */
669 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_H,
670 0x003f0000 | pvtpll->length);
671 /* set cal cnt = 24, T = 1us */
672 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON1,
673 0x18);
674 /* enable pvtpll */
675 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
676 0x00020002);
677 /* start monitor */
678 mmio_write_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_CON0_L,
679 0x00010001);
680 /* set core mux pvtpll */
681 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2),
682 CPUB01_PVTPLL_PATH_PVTPLL);
683 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
684 CPUB01_CLK_PATH_B0_PVTPLL);
685 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1),
686 CPUB01_CLK_PATH_B1_PVTPLL);
687 goto out;
688 }
689
690 /* set clk coreb23 div */
691 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;
692 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
693 CLKDIV_5BITS_SHF(div, 8));
694 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1),
695 CLKDIV_5BITS_SHF(div, 0));
696 /* set coreb23 mux gpll */
697 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
698 CPUB01_CLK_PATH_NOR_GPLL);
699 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
700 CPUB01_CLK_PATH_B0PLL);
701 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(1),
702 CPUB01_CLK_PATH_B1PLL);
703
704 out:
705 clk_scmi_b1pll_disable();
706
707 return 0;
708 }
709
clk_scmi_cpub23_set_rate(rk_scmi_clock_t * clock,unsigned long rate)710 static int clk_scmi_cpub23_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
711 {
712 int ret;
713
714 if (rate == 0)
715 return SCMI_INVALID_PARAMETERS;
716
717 ret = clk_cpub23_set_rate(rate, PLL_SEL_AUTO);
718 if (ret == 0)
719 sys_clk_info.cpub23_rate = rate;
720
721 return ret;
722 }
723
rk3588_b1pll_get_rate(void)724 static unsigned long rk3588_b1pll_get_rate(void)
725 {
726 unsigned int m, p, s, k;
727 uint64_t rate64 = 24000000, postdiv;
728 int mode;
729
730 mode = (mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0)) >> 6) &
731 0x3;
732
733 if (mode == 0)
734 return rate64;
735
736 m = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(8)) >>
737 CRU_PLLCON0_M_SHIFT) &
738 CRU_PLLCON0_M_MASK;
739 p = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >>
740 CRU_PLLCON1_P_SHIFT) &
741 CRU_PLLCON1_P_MASK;
742 s = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(9)) >>
743 CRU_PLLCON1_S_SHIFT) &
744 CRU_PLLCON1_S_MASK;
745 k = (mmio_read_32(BIGCORE1CRU_BASE + CRU_PLL_CON(10)) >>
746 CRU_PLLCON2_K_SHIFT) &
747 CRU_PLLCON2_K_MASK;
748
749 rate64 *= m;
750 rate64 = rate64 / p;
751
752 if (k != 0) {
753 /* fractional mode */
754 uint64_t frac_rate64 = 24000000 * k;
755
756 postdiv = p * 65535;
757 frac_rate64 = frac_rate64 / postdiv;
758 rate64 += frac_rate64;
759 }
760 rate64 = rate64 >> s;
761
762 return (unsigned long)rate64;
763 }
764
clk_scmi_cpub23_get_rate(rk_scmi_clock_t * clock)765 static unsigned long clk_scmi_cpub23_get_rate(rk_scmi_clock_t *clock)
766 {
767 int value, src, div;
768
769 value = mmio_read_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0));
770 src = (value & 0x6000) >> 13;
771 if (src == 2) {
772 udelay(2);
773 return (mmio_read_32(BIGCORE1GRF_BASE + RK3588_CPUB_PVTPLL_STATUS) & 0x3FFF) * MHz;
774 } else {
775 src = (value & 0x00c0) >> 6;
776 div = (value & 0x1f00) >> 8;
777 switch (src) {
778 case 0:
779 return 24000000;
780 case 1:
781 /* Make the return rate is equal to the set rate */
782 if (sys_clk_info.cpub23_rate)
783 return sys_clk_info.cpub23_rate;
784 else
785 return GPLL_RATE / (div + 1);
786 case 2:
787 return rk3588_b1pll_get_rate();
788 default:
789 return 0;
790 }
791 }
792 }
793
clk_scmi_cpub23_set_status(rk_scmi_clock_t * clock,bool status)794 static int clk_scmi_cpub23_set_status(rk_scmi_clock_t *clock, bool status)
795 {
796 return 0;
797 }
798
clk_scmi_dsu_get_rate(rk_scmi_clock_t * clock)799 static unsigned long clk_scmi_dsu_get_rate(rk_scmi_clock_t *clock)
800 {
801 int src, div;
802
803 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(1)) & 0x1;
804 if (src != 0) {
805 udelay(2);
806 return (mmio_read_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_STATUS) & 0x3FFF) * MHz;
807 } else {
808 src = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0x3000;
809 src = src >> 12;
810 div = mmio_read_32(DSUCRU_BASE + CRU_CLKSEL_CON(0)) & 0xf80;
811 div = div >> 7;
812 switch (src) {
813 case 0:
814 return rk3588_b0pll_get_rate() / (div + 1);
815 case 1:
816 return rk3588_b1pll_get_rate() / (div + 1);
817 case 2:
818 return rk3588_lpll_get_rate() / (div + 1);
819 case 3:
820 return GPLL_RATE / (div + 1);
821 default:
822 return 0;
823 }
824 }
825 }
826
clk_scmi_lpll_disable(void)827 static void clk_scmi_lpll_disable(void)
828 {
829 static bool is_lpll_disabled;
830
831 if (is_lpll_disabled)
832 return;
833
834 /* set corel mux gpll */
835 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5),
836 CPUL_CLK_PATH_NOR_GPLL);
837 /* set dsu mux gpll */
838 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),
839 SCLK_DSU_PATH_NOR_GPLL);
840 /* pll enter slow mode */
841 mmio_write_32(DSUCRU_BASE + CRU_MODE_CON0, CPU_PLL_PATH_SLOWMODE);
842 /* set pll power down */
843 mmio_write_32(DSUCRU_BASE + CRU_PLL_CON(17), CRU_PLL_POWER_DOWN);
844
845 is_lpll_disabled = true;
846 }
847
clk_dsu_set_rate(unsigned long rate,enum pll_type_sel type)848 static int clk_dsu_set_rate(unsigned long rate, enum pll_type_sel type)
849 {
850 struct pvtpll_table *pvtpll;
851 int div;
852
853 if (rate == 0)
854 return SCMI_INVALID_PARAMETERS;
855
856 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.cpul_table,
857 sys_clk_info.cpul_rate_count, rate);
858 if (pvtpll == NULL)
859 return SCMI_INVALID_PARAMETERS;
860
861 /* set pvtpll */
862 if (PVTPLL_NEED(type, pvtpll->length)) {
863 /* set clock gating interval */
864 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON2,
865 0x00040000);
866 /* set ring sel */
867 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L,
868 0x07000000 | (pvtpll->ring_sel << 8));
869 /* set length */
870 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_H,
871 0x003f0000 | pvtpll->length);
872 /* set cal cnt = 24, T = 1us */
873 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON1,
874 0x18);
875 /* enable pvtpll */
876 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L,
877 0x00020002);
878 /* start monitor */
879 mmio_write_32(DSUGRF_BASE + RK3588_DSU_PVTPLL_CON0_L,
880 0x00010001);
881 /* set dsu mux pvtpll */
882 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(7),
883 DSU_PVTPLL_PATH_PVTPLL);
884 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1),
885 SCLK_DSU_PATH_PVTPLL);
886 goto out;
887 }
888 /* set dsu div */
889 div = DIV_ROUND_UP(GPLL_RATE, rate) - 1;
890 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),
891 CLKDIV_5BITS_SHF(div, 7));
892 /* set dsu mux gpll */
893 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(0),
894 SCLK_DSU_PATH_NOR_GPLL);
895 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(1),
896 SCLK_DSU_PATH_NOR_PLL);
897
898 out:
899 clk_scmi_lpll_disable();
900
901 return 0;
902 }
903
clk_scmi_dsu_set_rate(rk_scmi_clock_t * clock,unsigned long rate)904 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
905 {
906 int ret;
907
908 if (rate == 0)
909 return SCMI_INVALID_PARAMETERS;
910
911 ret = clk_dsu_set_rate(rate, PLL_SEL_AUTO);
912
913 if (ret == 0)
914 sys_clk_info.dsu_rate = rate;
915 return ret;
916 }
917
clk_scmi_dsu_set_status(rk_scmi_clock_t * clock,bool status)918 static int clk_scmi_dsu_set_status(rk_scmi_clock_t *clock, bool status)
919 {
920 return 0;
921 }
922
clk_scmi_gpu_get_rate(rk_scmi_clock_t * clock)923 static unsigned long clk_scmi_gpu_get_rate(rk_scmi_clock_t *clock)
924 {
925 int div, src;
926
927 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x4000) != 0) {
928 udelay(2);
929 return (mmio_read_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_STATUS) & 0x3FFF) * MHz;
930 } else {
931 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x1f;
932 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x00e0;
933 src = src >> 5;
934 switch (src) {
935 case 0:
936 /* Make the return rate is equal to the set rate */
937 if (sys_clk_info.gpu_rate)
938 return sys_clk_info.gpu_rate;
939 else
940 return GPLL_RATE / (div + 1);
941 case 1:
942 return CPLL_RATE / (div + 1);
943 case 2:
944 return AUPLL_RATE / (div + 1);
945 case 3:
946 return NPLL_RATE / (div + 1);
947 case 4:
948 return SPLL_RATE / (div + 1);
949 default:
950 return 0;
951 }
952 }
953 }
954
clk_gpu_set_rate(unsigned long rate,enum pll_type_sel type)955 static int clk_gpu_set_rate(unsigned long rate, enum pll_type_sel type)
956 {
957 struct pvtpll_table *pvtpll;
958 int div;
959
960 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.gpu_table,
961 sys_clk_info.gpu_rate_count, rate);
962 if (pvtpll == NULL)
963 return SCMI_INVALID_PARAMETERS;
964
965 if (PVTPLL_NEED(type, pvtpll->length)) {
966 /* set clock gating interval */
967 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON2,
968 0x00040000);
969 /* set ring sel */
970 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L,
971 0x07000000 | (pvtpll->ring_sel << 8));
972 /* set length */
973 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_H,
974 0x003f0000 | pvtpll->length);
975 /* set cal cnt = 24, T = 1us */
976 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON1,
977 0x18);
978 /* enable pvtpll */
979 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L,
980 0x00020002);
981 /* start monitor */
982 mmio_write_32(GPUGRF_BASE + RK3588_GPU_PVTPLL_CON0_L,
983 0x00010001);
984 /* set gpu mux pvtpll */
985 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158),
986 GPU_CLK_PATH_PVTPLL);
987 return 0;
988 }
989
990 /* set gpu div */
991 div = DIV_ROUND_UP(GPLL_RATE, rate);
992 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158),
993 CLKDIV_5BITS_SHF(div - 1, 0));
994 /* set gpu mux gpll */
995 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158),
996 GPU_CLK_PATH_NOR_GPLL);
997 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158),
998 GPU_CLK_PATH_NOR_PLL);
999
1000 return 0;
1001 }
1002
clk_scmi_gpu_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1003 static int clk_scmi_gpu_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1004 {
1005 int ret;
1006
1007 if (rate == 0)
1008 return SCMI_INVALID_PARAMETERS;
1009
1010 ret = clk_gpu_set_rate(rate, PLL_SEL_AUTO);
1011 if (ret == 0)
1012 sys_clk_info.gpu_rate = rate;
1013
1014 return ret;
1015 }
1016
clk_scmi_gpu_set_status(rk_scmi_clock_t * clock,bool status)1017 static int clk_scmi_gpu_set_status(rk_scmi_clock_t *clock, bool status)
1018 {
1019 return 0;
1020 }
1021
clk_scmi_npu_get_rate(rk_scmi_clock_t * clock)1022 static unsigned long clk_scmi_npu_get_rate(rk_scmi_clock_t *clock)
1023 {
1024 int div, src;
1025
1026 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(74)) & 0x1) != 0) {
1027 udelay(2);
1028 return (mmio_read_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_STATUS) & 0x3FFF) * MHz;
1029 } else {
1030 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x007c;
1031 div = div >> 2;
1032 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x0380;
1033 src = src >> 7;
1034 switch (src) {
1035 case 0:
1036 /* Make the return rate is equal to the set rate */
1037 if (sys_clk_info.npu_rate != 0)
1038 return sys_clk_info.npu_rate;
1039 else
1040 return GPLL_RATE / (div + 1);
1041 case 1:
1042 return CPLL_RATE / (div + 1);
1043 case 2:
1044 return AUPLL_RATE / (div + 1);
1045 case 3:
1046 return NPLL_RATE / (div + 1);
1047 case 4:
1048 return SPLL_RATE / (div + 1);
1049 default:
1050 return 0;
1051 }
1052 }
1053 }
1054
clk_npu_set_rate(unsigned long rate,enum pll_type_sel type)1055 static int clk_npu_set_rate(unsigned long rate, enum pll_type_sel type)
1056 {
1057 struct pvtpll_table *pvtpll;
1058 int div;
1059
1060 pvtpll = rkclk_get_pvtpll_config(sys_clk_info.npu_table,
1061 sys_clk_info.npu_rate_count, rate);
1062 if (pvtpll == NULL)
1063 return SCMI_INVALID_PARAMETERS;
1064
1065 if (PVTPLL_NEED(type, pvtpll->length)) {
1066 /* set clock gating interval */
1067 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON2,
1068 0x00040000);
1069 /* set ring sel */
1070 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L,
1071 0x07000000 | (pvtpll->ring_sel << 8));
1072 /* set length */
1073 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_H,
1074 0x003f0000 | pvtpll->length);
1075 /* set cal cnt = 24, T = 1us */
1076 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON1,
1077 0x18);
1078 /* enable pvtpll */
1079 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L,
1080 0x00020002);
1081 /* start monitor */
1082 mmio_write_32(NPUGRF_BASE + RK3588_NPU_PVTPLL_CON0_L,
1083 0x00010001);
1084 /* set npu mux pvtpll */
1085 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74),
1086 NPU_CLK_PATH_PVTPLL);
1087 return 0;
1088 }
1089
1090 /* set npu div */
1091 div = DIV_ROUND_UP(GPLL_RATE, rate);
1092 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73),
1093 CLKDIV_5BITS_SHF(div - 1, 2));
1094 /* set npu mux gpll */
1095 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(73),
1096 NPU_CLK_PATH_NOR_GPLL);
1097 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(74),
1098 NPU_CLK_PATH_NOR_PLL);
1099
1100 return 0;
1101 }
1102
clk_scmi_npu_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1103 static int clk_scmi_npu_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1104 {
1105 int ret;
1106
1107 if (rate == 0)
1108 return SCMI_INVALID_PARAMETERS;
1109
1110 ret = clk_npu_set_rate(rate, PLL_SEL_AUTO);
1111 if (ret == 0)
1112 sys_clk_info.npu_rate = rate;
1113
1114 return ret;
1115 }
1116
clk_scmi_npu_set_status(rk_scmi_clock_t * clock,bool status)1117 static int clk_scmi_npu_set_status(rk_scmi_clock_t *clock, bool status)
1118 {
1119 return 0;
1120 }
1121
clk_scmi_sbus_get_rate(rk_scmi_clock_t * clock)1122 static unsigned long clk_scmi_sbus_get_rate(rk_scmi_clock_t *clock)
1123 {
1124 int div;
1125
1126 if ((mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0)) & 0x0800) != 0) {
1127 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0));
1128 div = (div & 0x03e0) >> 5;
1129 return SPLL_RATE / (div + 1);
1130 } else {
1131 return OSC_HZ;
1132 }
1133 }
1134
clk_scmi_sbus_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1135 static int clk_scmi_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1136 {
1137 int div;
1138
1139 if (rate == OSC_HZ) {
1140 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0),
1141 WMSK_BIT(11));
1142 return 0;
1143 }
1144
1145 div = DIV_ROUND_UP(SPLL_RATE, rate);
1146 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0),
1147 CLKDIV_5BITS_SHF(div - 1, 5));
1148 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0),
1149 BIT_WITH_WMSK(11) | WMSK_BIT(10));
1150 return 0;
1151 }
1152
clk_scmi_sbus_set_status(rk_scmi_clock_t * clock,bool status)1153 static int clk_scmi_sbus_set_status(rk_scmi_clock_t *clock, bool status)
1154 {
1155 return 0;
1156 }
1157
clk_scmi_pclk_sbus_get_rate(rk_scmi_clock_t * clock)1158 static unsigned long clk_scmi_pclk_sbus_get_rate(rk_scmi_clock_t *clock)
1159 {
1160 int div;
1161
1162 div = mmio_read_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0));
1163 div = div & 0x001f;
1164 return SPLL_RATE / (div + 1);
1165
1166 }
1167
clk_scmi_pclk_sbus_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1168 static int clk_scmi_pclk_sbus_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1169 {
1170 int div;
1171
1172 div = DIV_ROUND_UP(SPLL_RATE, rate);
1173 mmio_write_32(BUSSCRU_BASE + CRU_CLKSEL_CON(0),
1174 CLKDIV_5BITS_SHF(div - 1, 0));
1175 return 0;
1176 }
1177
clk_scmi_pclk_sbus_set_status(rk_scmi_clock_t * clock,bool status)1178 static int clk_scmi_pclk_sbus_set_status(rk_scmi_clock_t *clock, bool status)
1179 {
1180 return 0;
1181 }
1182
clk_scmi_cclk_sdmmc_get_rate(rk_scmi_clock_t * clock)1183 static unsigned long clk_scmi_cclk_sdmmc_get_rate(rk_scmi_clock_t *clock)
1184 {
1185 int div;
1186 uint32_t src;
1187
1188 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x3000;
1189 src = src >> 12;
1190 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0fc0;
1191 div = div >> 6;
1192 if (src == 1) {
1193 return SPLL_RATE / (div + 1);
1194 } else if (src == 2) {
1195 return OSC_HZ / (div + 1);
1196 } else {
1197 return GPLL_RATE / (div + 1);
1198 }
1199 }
1200
clk_scmi_cclk_sdmmc_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1201 static int clk_scmi_cclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1202 {
1203 int div;
1204
1205 if ((OSC_HZ % rate) == 0) {
1206 div = DIV_ROUND_UP(OSC_HZ, rate);
1207 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3),
1208 CLKDIV_6BITS_SHF(div - 1, 6) |
1209 BITS_WITH_WMASK(2U, 0x3U, 12));
1210 } else if ((SPLL_RATE % rate) == 0) {
1211 div = DIV_ROUND_UP(SPLL_RATE, rate);
1212 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3),
1213 CLKDIV_6BITS_SHF(div - 1, 6) |
1214 BITS_WITH_WMASK(1U, 0x3U, 12));
1215 } else {
1216 div = DIV_ROUND_UP(GPLL_RATE, rate);
1217 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3),
1218 CLKDIV_6BITS_SHF(div - 1, 6) |
1219 BITS_WITH_WMASK(0U, 0x3U, 12));
1220 }
1221
1222 return 0;
1223 }
1224
clk_scmi_cclk_sdmmc_set_status(rk_scmi_clock_t * clock,bool status)1225 static int clk_scmi_cclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status)
1226 {
1227 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3),
1228 BITS_WITH_WMASK(!status, 0x1U, 4));
1229 return 0;
1230 }
1231
clk_scmi_dclk_sdmmc_get_rate(rk_scmi_clock_t * clock)1232 static unsigned long clk_scmi_dclk_sdmmc_get_rate(rk_scmi_clock_t *clock)
1233 {
1234 int div;
1235 uint32_t src;
1236
1237 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0020;
1238 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x001f;
1239 if (src != 0) {
1240 return SPLL_RATE / (div + 1);
1241 } else {
1242 return GPLL_RATE / (div + 1);
1243 }
1244 }
1245
clk_scmi_dclk_sdmmc_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1246 static int clk_scmi_dclk_sdmmc_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1247 {
1248 int div;
1249
1250 if ((SPLL_RATE % rate) == 0) {
1251 div = DIV_ROUND_UP(SPLL_RATE, rate);
1252 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3),
1253 CLKDIV_5BITS_SHF(div - 1, 0) |
1254 BITS_WITH_WMASK(1U, 0x1U, 5));
1255 } else {
1256 div = DIV_ROUND_UP(GPLL_RATE, rate);
1257 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3),
1258 CLKDIV_5BITS_SHF(div - 1, 0) |
1259 BITS_WITH_WMASK(0U, 0x1U, 5));
1260 }
1261 return 0;
1262 }
1263
clk_scmi_dclk_sdmmc_set_status(rk_scmi_clock_t * clock,bool status)1264 static int clk_scmi_dclk_sdmmc_set_status(rk_scmi_clock_t *clock, bool status)
1265 {
1266 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3),
1267 BITS_WITH_WMASK(!status, 0x1U, 1));
1268 return 0;
1269 }
1270
clk_scmi_aclk_secure_ns_get_rate(rk_scmi_clock_t * clock)1271 static unsigned long clk_scmi_aclk_secure_ns_get_rate(rk_scmi_clock_t *clock)
1272 {
1273 uint32_t src;
1274
1275 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0003;
1276 switch (src) {
1277 case 0:
1278 return 350 * MHz;
1279 case 1:
1280 return 200 * MHz;
1281 case 2:
1282 return 100 * MHz;
1283 case 3:
1284 return OSC_HZ;
1285 default:
1286 return 0;
1287 }
1288 }
1289
clk_scmi_aclk_secure_ns_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1290 static int clk_scmi_aclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1291 {
1292 uint32_t src;
1293
1294 if (rate >= 350 * MHz)
1295 src = 0;
1296 else if (rate >= 200 * MHz)
1297 src = 1;
1298 else if (rate >= 100 * MHz)
1299 src = 2;
1300 else
1301 src = 3;
1302
1303 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1304 BITS_WITH_WMASK(src, 0x3U, 0));
1305
1306 return 0;
1307 }
1308
clk_scmi_aclk_secure_ns_set_status(rk_scmi_clock_t * clock,bool status)1309 static int clk_scmi_aclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status)
1310 {
1311 return 0;
1312 }
1313
clk_scmi_hclk_secure_ns_get_rate(rk_scmi_clock_t * clock)1314 static unsigned long clk_scmi_hclk_secure_ns_get_rate(rk_scmi_clock_t *clock)
1315 {
1316 uint32_t src;
1317
1318 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x000c;
1319 src = src >> 2;
1320 switch (src) {
1321 case 0:
1322 return 150 * MHz;
1323 case 1:
1324 return 100 * MHz;
1325 case 2:
1326 return 50 * MHz;
1327 case 3:
1328 return OSC_HZ;
1329 default:
1330 return 0;
1331 }
1332 }
1333
clk_scmi_hclk_secure_ns_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1334 static int clk_scmi_hclk_secure_ns_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1335 {
1336 uint32_t src;
1337
1338 if (rate >= 150 * MHz)
1339 src = 0;
1340 else if (rate >= 100 * MHz)
1341 src = 1;
1342 else if (rate >= 50 * MHz)
1343 src = 2;
1344 else
1345 src = 3;
1346
1347 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1348 BITS_WITH_WMASK(src, 0x3U, 2));
1349 return 0;
1350 }
1351
clk_scmi_hclk_secure_ns_set_status(rk_scmi_clock_t * clock,bool status)1352 static int clk_scmi_hclk_secure_ns_set_status(rk_scmi_clock_t *clock, bool status)
1353 {
1354 return 0;
1355 }
1356
clk_scmi_tclk_wdt_get_rate(rk_scmi_clock_t * clock)1357 static unsigned long clk_scmi_tclk_wdt_get_rate(rk_scmi_clock_t *clock)
1358 {
1359 return OSC_HZ;
1360 }
1361
clk_scmi_tclk_wdt_set_status(rk_scmi_clock_t * clock,bool status)1362 static int clk_scmi_tclk_wdt_set_status(rk_scmi_clock_t *clock, bool status)
1363 {
1364 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2),
1365 BITS_WITH_WMASK(!status, 0x1U, 0));
1366 return 0;
1367 }
1368
clk_scmi_keyladder_core_get_rate(rk_scmi_clock_t * clock)1369 static unsigned long clk_scmi_keyladder_core_get_rate(rk_scmi_clock_t *clock)
1370 {
1371 uint32_t src;
1372
1373 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x00c0;
1374 src = src >> 6;
1375 switch (src) {
1376 case 0:
1377 return 350 * MHz;
1378 case 1:
1379 return 233 * MHz;
1380 case 2:
1381 return 116 * MHz;
1382 case 3:
1383 return OSC_HZ;
1384 default:
1385 return 0;
1386 }
1387 }
1388
clk_scmi_keyladder_core_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1389 static int clk_scmi_keyladder_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1390 {
1391 uint32_t src;
1392
1393 if (rate >= 350 * MHz)
1394 src = 0;
1395 else if (rate >= 233 * MHz)
1396 src = 1;
1397 else if (rate >= 116 * MHz)
1398 src = 2;
1399 else
1400 src = 3;
1401
1402 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2),
1403 BITS_WITH_WMASK(src, 0x3U, 6));
1404 return 0;
1405 }
1406
clk_scmi_keyladder_core_set_status(rk_scmi_clock_t * clock,bool status)1407 static int clk_scmi_keyladder_core_set_status(rk_scmi_clock_t *clock, bool status)
1408 {
1409 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1410 BITS_WITH_WMASK(!status, 0x1U, 9));
1411 return 0;
1412 }
1413
clk_scmi_keyladder_rng_get_rate(rk_scmi_clock_t * clock)1414 static unsigned long clk_scmi_keyladder_rng_get_rate(rk_scmi_clock_t *clock)
1415 {
1416 uint32_t src;
1417
1418 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0300;
1419 src = src >> 8;
1420 switch (src) {
1421 case 0:
1422 return 175 * MHz;
1423 case 1:
1424 return 116 * MHz;
1425 case 2:
1426 return 58 * MHz;
1427 case 3:
1428 return OSC_HZ;
1429 default:
1430 return 0;
1431 }
1432 }
1433
clk_scmi_keyladder_rng_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1434 static int clk_scmi_keyladder_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1435 {
1436 uint32_t src;
1437
1438 if (rate >= 175 * MHz)
1439 src = 0;
1440 else if (rate >= 116 * MHz)
1441 src = 1;
1442 else if (rate >= 58 * MHz)
1443 src = 2;
1444 else
1445 src = 3;
1446
1447 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2),
1448 BITS_WITH_WMASK(src, 0x3U, 8));
1449 return 0;
1450 }
1451
clk_scmi_keyladder_rng_set_status(rk_scmi_clock_t * clock,bool status)1452 static int clk_scmi_keyladder_rng_set_status(rk_scmi_clock_t *clock, bool status)
1453 {
1454 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1455 BITS_WITH_WMASK(!status, 0x1U, 10));
1456 return 0;
1457 }
1458
clk_scmi_aclk_secure_s_get_rate(rk_scmi_clock_t * clock)1459 static unsigned long clk_scmi_aclk_secure_s_get_rate(rk_scmi_clock_t *clock)
1460 {
1461 uint32_t src;
1462
1463 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0030;
1464 src = src >> 4;
1465 switch (src) {
1466 case 0:
1467 return 350 * MHz;
1468 case 1:
1469 return 233 * MHz;
1470 case 2:
1471 return 116 * MHz;
1472 case 3:
1473 return OSC_HZ;
1474 default:
1475 return 0;
1476 }
1477 }
1478
clk_scmi_aclk_secure_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1479 static int clk_scmi_aclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1480 {
1481 uint32_t src;
1482
1483 if (rate >= 350 * MHz)
1484 src = 0;
1485 else if (rate >= 233 * MHz)
1486 src = 1;
1487 else if (rate >= 116 * MHz)
1488 src = 2;
1489 else
1490 src = 3;
1491
1492 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1493 BITS_WITH_WMASK(src, 0x3U, 4));
1494 return 0;
1495 }
1496
clk_scmi_aclk_secure_s_set_status(rk_scmi_clock_t * clock,bool status)1497 static int clk_scmi_aclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status)
1498 {
1499 return 0;
1500 }
1501
clk_scmi_hclk_secure_s_get_rate(rk_scmi_clock_t * clock)1502 static unsigned long clk_scmi_hclk_secure_s_get_rate(rk_scmi_clock_t *clock)
1503 {
1504 uint32_t src;
1505
1506 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x00c0;
1507 src = src >> 6;
1508 switch (src) {
1509 case 0:
1510 return 175 * MHz;
1511 case 1:
1512 return 116 * MHz;
1513 case 2:
1514 return 58 * MHz;
1515 case 3:
1516 return OSC_HZ;
1517 default:
1518 return 0;
1519 }
1520 }
1521
clk_scmi_hclk_secure_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1522 static int clk_scmi_hclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1523 {
1524 uint32_t src;
1525
1526 if (rate >= 175 * MHz)
1527 src = 0;
1528 else if (rate >= 116 * MHz)
1529 src = 1;
1530 else if (rate >= 58 * MHz)
1531 src = 2;
1532 else
1533 src = 3;
1534
1535 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1536 BITS_WITH_WMASK(src, 0x3U, 6));
1537 return 0;
1538 }
1539
clk_scmi_hclk_secure_s_set_status(rk_scmi_clock_t * clock,bool status)1540 static int clk_scmi_hclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status)
1541 {
1542 return 0;
1543 }
1544
clk_scmi_pclk_secure_s_get_rate(rk_scmi_clock_t * clock)1545 static unsigned long clk_scmi_pclk_secure_s_get_rate(rk_scmi_clock_t *clock)
1546 {
1547 uint32_t src;
1548
1549 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0300;
1550 src = src >> 8;
1551 switch (src) {
1552 case 0:
1553 return 116 * MHz;
1554 case 1:
1555 return 58 * MHz;
1556 case 2:
1557 return OSC_HZ;
1558 default:
1559 return 0;
1560 }
1561 }
1562
clk_scmi_pclk_secure_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1563 static int clk_scmi_pclk_secure_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1564 {
1565 uint32_t src;
1566
1567 if (rate >= 116 * MHz)
1568 src = 0;
1569 else if (rate >= 58 * MHz)
1570 src = 1;
1571 else
1572 src = 2;
1573
1574 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1575 BITS_WITH_WMASK(src, 0x3U, 8));
1576 return 0;
1577 }
1578
clk_scmi_pclk_secure_s_set_status(rk_scmi_clock_t * clock,bool status)1579 static int clk_scmi_pclk_secure_s_set_status(rk_scmi_clock_t *clock, bool status)
1580 {
1581 return 0;
1582 }
1583
clk_scmi_crypto_rng_get_rate(rk_scmi_clock_t * clock)1584 static unsigned long clk_scmi_crypto_rng_get_rate(rk_scmi_clock_t *clock)
1585 {
1586 uint32_t src;
1587
1588 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0xc000;
1589 src = src >> 14;
1590 switch (src) {
1591 case 0:
1592 return 175 * MHz;
1593 case 1:
1594 return 116 * MHz;
1595 case 2:
1596 return 58 * MHz;
1597 case 3:
1598 return OSC_HZ;
1599 default:
1600 return 0;
1601 }
1602 }
1603
clk_scmi_crypto_rng_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1604 static int clk_scmi_crypto_rng_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1605 {
1606 uint32_t src;
1607
1608 if (rate >= 175 * MHz)
1609 src = 0;
1610 else if (rate >= 116 * MHz)
1611 src = 1;
1612 else if (rate >= 58 * MHz)
1613 src = 2;
1614 else
1615 src = 3;
1616
1617 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1618 BITS_WITH_WMASK(src, 0x3U, 14));
1619 return 0;
1620 }
1621
clk_scmi_crypto_rng_set_status(rk_scmi_clock_t * clock,bool status)1622 static int clk_scmi_crypto_rng_set_status(rk_scmi_clock_t *clock, bool status)
1623 {
1624 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1625 BITS_WITH_WMASK(!status, 0x1U, 1));
1626
1627 return 0;
1628 }
1629
clk_scmi_crypto_core_get_rate(rk_scmi_clock_t * clock)1630 static unsigned long clk_scmi_crypto_core_get_rate(rk_scmi_clock_t *clock)
1631 {
1632 uint32_t src;
1633
1634 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x0c00;
1635 src = src >> 10;
1636 switch (src) {
1637 case 0:
1638 return 350 * MHz;
1639 case 1:
1640 return 233 * MHz;
1641 case 2:
1642 return 116 * MHz;
1643 case 3:
1644 return OSC_HZ;
1645 default:
1646 return 0;
1647 }
1648 }
1649
clk_scmi_crypto_core_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1650 static int clk_scmi_crypto_core_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1651 {
1652 uint32_t src;
1653
1654 if (rate >= 350 * MHz)
1655 src = 0;
1656 else if (rate >= 233 * MHz)
1657 src = 1;
1658 else if (rate >= 116 * MHz)
1659 src = 2;
1660 else
1661 src = 3;
1662
1663 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1664 BITS_WITH_WMASK(src, 0x3U, 10));
1665 return 0;
1666 }
1667
clk_scmi_crypto_core_set_status(rk_scmi_clock_t * clock,bool status)1668 static int clk_scmi_crypto_core_set_status(rk_scmi_clock_t *clock, bool status)
1669 {
1670 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(0),
1671 BITS_WITH_WMASK(!status, 0x1U, 15));
1672
1673 return 0;
1674 }
1675
clk_scmi_crypto_pka_get_rate(rk_scmi_clock_t * clock)1676 static unsigned long clk_scmi_crypto_pka_get_rate(rk_scmi_clock_t *clock)
1677 {
1678 uint32_t src;
1679
1680 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(1)) & 0x3000;
1681 src = src >> 12;
1682 switch (src) {
1683 case 0:
1684 return 350 * MHz;
1685 case 1:
1686 return 233 * MHz;
1687 case 2:
1688 return 116 * MHz;
1689 case 3:
1690 return OSC_HZ;
1691 default:
1692 return 0;
1693 }
1694 }
1695
clk_scmi_crypto_pka_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1696 static int clk_scmi_crypto_pka_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1697 {
1698 uint32_t src;
1699
1700 if (rate >= 350 * MHz)
1701 src = 0;
1702 else if (rate >= 233 * MHz)
1703 src = 1;
1704 else if (rate >= 116 * MHz)
1705 src = 2;
1706 else
1707 src = 3;
1708
1709 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(1),
1710 BITS_WITH_WMASK(src, 0x3U, 12));
1711 return 0;
1712 }
1713
clk_scmi_crypto_pka_set_status(rk_scmi_clock_t * clock,bool status)1714 static int clk_scmi_crypto_pka_set_status(rk_scmi_clock_t *clock, bool status)
1715 {
1716 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1717 BITS_WITH_WMASK(!status, 0x1U, 0));
1718
1719 return 0;
1720 }
1721
clk_scmi_spll_get_rate(rk_scmi_clock_t * clock)1722 static unsigned long clk_scmi_spll_get_rate(rk_scmi_clock_t *clock)
1723 {
1724 uint32_t src;
1725
1726 src = mmio_read_32(BUSSCRU_BASE + CRU_MODE_CON0) & 0x3;
1727 switch (src) {
1728 case 0:
1729 return OSC_HZ;
1730 case 1:
1731 return 702 * MHz;
1732 case 2:
1733 return 32768;
1734 default:
1735 return 0;
1736 }
1737 }
1738
clk_scmi_spll_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1739 static int clk_scmi_spll_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1740 {
1741 uint32_t src;
1742
1743 if (rate >= 700 * MHz)
1744 src = 1;
1745 else
1746 src = 0;
1747
1748 mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0,
1749 BITS_WITH_WMASK(0, 0x3U, 0));
1750 mmio_write_32(BUSSCRU_BASE + CRU_PLL_CON(137),
1751 BITS_WITH_WMASK(2, 0x7U, 6));
1752
1753 mmio_write_32(BUSSCRU_BASE + CRU_MODE_CON0,
1754 BITS_WITH_WMASK(src, 0x3U, 0));
1755 return 0;
1756 }
1757
clk_scmi_spll_set_status(rk_scmi_clock_t * clock,bool status)1758 static int clk_scmi_spll_set_status(rk_scmi_clock_t *clock, bool status)
1759 {
1760 return 0;
1761 }
1762
clk_scmi_hclk_sd_get_rate(rk_scmi_clock_t * clock)1763 static unsigned long clk_scmi_hclk_sd_get_rate(rk_scmi_clock_t *clock)
1764 {
1765 return clk_scmi_hclk_secure_ns_get_rate(clock);
1766 }
1767
clk_scmi_hclk_sd_set_status(rk_scmi_clock_t * clock,bool status)1768 static int clk_scmi_hclk_sd_set_status(rk_scmi_clock_t *clock, bool status)
1769 {
1770 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3),
1771 BITS_WITH_WMASK(!status, 0x1U, 2));
1772 return 0;
1773 }
1774
clk_scmi_crypto_rng_s_get_rate(rk_scmi_clock_t * clock)1775 static unsigned long clk_scmi_crypto_rng_s_get_rate(rk_scmi_clock_t *clock)
1776 {
1777 uint32_t src;
1778
1779 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x0030;
1780 src = src >> 4;
1781 switch (src) {
1782 case 0:
1783 return 175 * MHz;
1784 case 1:
1785 return 116 * MHz;
1786 case 2:
1787 return 58 * MHz;
1788 case 3:
1789 return OSC_HZ;
1790 default:
1791 return 0;
1792 }
1793 }
1794
clk_scmi_crypto_rng_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1795 static int clk_scmi_crypto_rng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1796 {
1797 uint32_t src;
1798
1799 if (rate >= 175 * MHz)
1800 src = 0;
1801 else if (rate >= 116 * MHz)
1802 src = 1;
1803 else if (rate >= 58 * MHz)
1804 src = 2;
1805 else
1806 src = 3;
1807
1808 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2),
1809 BITS_WITH_WMASK(src, 0x3U, 4));
1810 return 0;
1811 }
1812
clk_scmi_crypto_rng_s_set_status(rk_scmi_clock_t * clock,bool status)1813 static int clk_scmi_crypto_rng_s_set_status(rk_scmi_clock_t *clock, bool status)
1814 {
1815 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1816 BITS_WITH_WMASK(!status, 0x1U, 6));
1817
1818 return 0;
1819 }
1820
clk_scmi_crypto_core_s_get_rate(rk_scmi_clock_t * clock)1821 static unsigned long clk_scmi_crypto_core_s_get_rate(rk_scmi_clock_t *clock)
1822 {
1823 uint32_t src;
1824
1825 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x3;
1826 src = src >> 0;
1827 switch (src) {
1828 case 0:
1829 return 350 * MHz;
1830 case 1:
1831 return 233 * MHz;
1832 case 2:
1833 return 116 * MHz;
1834 case 3:
1835 return OSC_HZ;
1836 default:
1837 return 0;
1838 }
1839 }
1840
clk_scmi_crypto_core_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1841 static int clk_scmi_crypto_core_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1842 {
1843 uint32_t src;
1844
1845 if (rate >= 350 * MHz)
1846 src = 0;
1847 else if (rate >= 233 * MHz)
1848 src = 1;
1849 else if (rate >= 116 * MHz)
1850 src = 2;
1851 else
1852 src = 3;
1853
1854 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2),
1855 BITS_WITH_WMASK(src, 0x3U, 0));
1856 return 0;
1857 }
1858
clk_scmi_crypto_core_s_set_status(rk_scmi_clock_t * clock,bool status)1859 static int clk_scmi_crypto_core_s_set_status(rk_scmi_clock_t *clock, bool status)
1860 {
1861 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1862 BITS_WITH_WMASK(!status, 0x1U, 4));
1863
1864 return 0;
1865 }
1866
clk_scmi_crypto_pka_s_get_rate(rk_scmi_clock_t * clock)1867 static unsigned long clk_scmi_crypto_pka_s_get_rate(rk_scmi_clock_t *clock)
1868 {
1869 uint32_t src;
1870
1871 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(2)) & 0x000c;
1872 src = src >> 2;
1873 switch (src) {
1874 case 0:
1875 return 350 * MHz;
1876 case 1:
1877 return 233 * MHz;
1878 case 2:
1879 return 116 * MHz;
1880 case 3:
1881 return OSC_HZ;
1882 default:
1883 return 0;
1884 }
1885 }
1886
clk_scmi_crypto_pka_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1887 static int clk_scmi_crypto_pka_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1888 {
1889 uint32_t src;
1890
1891 if (rate >= 350 * MHz)
1892 src = 0;
1893 else if (rate >= 233 * MHz)
1894 src = 1;
1895 else if (rate >= 116 * MHz)
1896 src = 2;
1897 else
1898 src = 3;
1899
1900 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(2),
1901 BITS_WITH_WMASK(src, 0x3U, 2));
1902 return 0;
1903 }
1904
clk_scmi_crypto_pka_s_set_status(rk_scmi_clock_t * clock,bool status)1905 static int clk_scmi_crypto_pka_s_set_status(rk_scmi_clock_t *clock, bool status)
1906 {
1907 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1908 BITS_WITH_WMASK(!status, 0x1U, 5));
1909
1910 return 0;
1911 }
1912
clk_scmi_a_crypto_s_get_rate(rk_scmi_clock_t * clock)1913 static unsigned long clk_scmi_a_crypto_s_get_rate(rk_scmi_clock_t *clock)
1914 {
1915 return clk_scmi_aclk_secure_s_get_rate(clock);
1916 }
1917
clk_scmi_a_crypto_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1918 static int clk_scmi_a_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1919 {
1920 return clk_scmi_aclk_secure_s_set_rate(clock, rate);
1921 }
1922
clk_scmi_a_crypto_s_set_status(rk_scmi_clock_t * clock,bool status)1923 static int clk_scmi_a_crypto_s_set_status(rk_scmi_clock_t *clock, bool status)
1924 {
1925 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1926 BITS_WITH_WMASK(!status, 0x1U, 7));
1927
1928 return 0;
1929 }
1930
clk_scmi_h_crypto_s_get_rate(rk_scmi_clock_t * clock)1931 static unsigned long clk_scmi_h_crypto_s_get_rate(rk_scmi_clock_t *clock)
1932 {
1933 return clk_scmi_hclk_secure_s_get_rate(clock);
1934 }
1935
clk_scmi_h_crypto_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1936 static int clk_scmi_h_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1937 {
1938 return clk_scmi_hclk_secure_s_set_rate(clock, rate);
1939 }
1940
clk_scmi_h_crypto_s_set_status(rk_scmi_clock_t * clock,bool status)1941 static int clk_scmi_h_crypto_s_set_status(rk_scmi_clock_t *clock, bool status)
1942 {
1943 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1944 BITS_WITH_WMASK(!status, 0x1U, 8));
1945
1946 return 0;
1947 }
1948
clk_scmi_p_crypto_s_get_rate(rk_scmi_clock_t * clock)1949 static unsigned long clk_scmi_p_crypto_s_get_rate(rk_scmi_clock_t *clock)
1950 {
1951 return clk_scmi_pclk_secure_s_get_rate(clock);
1952 }
1953
clk_scmi_p_crypto_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1954 static int clk_scmi_p_crypto_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1955 {
1956 return clk_scmi_pclk_secure_s_set_rate(clock, rate);
1957 }
1958
clk_scmi_p_crypto_s_set_status(rk_scmi_clock_t * clock,bool status)1959 static int clk_scmi_p_crypto_s_set_status(rk_scmi_clock_t *clock, bool status)
1960 {
1961 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2),
1962 BITS_WITH_WMASK(!status, 0x1U, 13));
1963
1964 return 0;
1965 }
1966
clk_scmi_a_keylad_s_get_rate(rk_scmi_clock_t * clock)1967 static unsigned long clk_scmi_a_keylad_s_get_rate(rk_scmi_clock_t *clock)
1968 {
1969 return clk_scmi_aclk_secure_s_get_rate(clock);
1970 }
1971
clk_scmi_a_keylad_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1972 static int clk_scmi_a_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1973 {
1974 return clk_scmi_aclk_secure_s_set_rate(clock, rate);
1975 }
1976
clk_scmi_a_keylad_s_set_status(rk_scmi_clock_t * clock,bool status)1977 static int clk_scmi_a_keylad_s_set_status(rk_scmi_clock_t *clock, bool status)
1978 {
1979 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1980 BITS_WITH_WMASK(!status, 0x1U, 11));
1981
1982 return 0;
1983 }
1984
clk_scmi_h_keylad_s_get_rate(rk_scmi_clock_t * clock)1985 static unsigned long clk_scmi_h_keylad_s_get_rate(rk_scmi_clock_t *clock)
1986 {
1987 return clk_scmi_hclk_secure_s_get_rate(clock);
1988 }
1989
clk_scmi_h_keylad_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)1990 static int clk_scmi_h_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
1991 {
1992 return clk_scmi_hclk_secure_s_set_rate(clock, rate);
1993 }
1994
clk_scmi_h_keylad_s_set_status(rk_scmi_clock_t * clock,bool status)1995 static int clk_scmi_h_keylad_s_set_status(rk_scmi_clock_t *clock, bool status)
1996 {
1997 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
1998 BITS_WITH_WMASK(!status, 0x1U, 12));
1999
2000 return 0;
2001 }
2002
clk_scmi_p_keylad_s_get_rate(rk_scmi_clock_t * clock)2003 static unsigned long clk_scmi_p_keylad_s_get_rate(rk_scmi_clock_t *clock)
2004 {
2005 return clk_scmi_pclk_secure_s_get_rate(clock);
2006 }
2007
clk_scmi_p_keylad_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)2008 static int clk_scmi_p_keylad_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
2009 {
2010 return clk_scmi_pclk_secure_s_set_rate(clock, rate);
2011 }
2012
clk_scmi_p_keylad_s_set_status(rk_scmi_clock_t * clock,bool status)2013 static int clk_scmi_p_keylad_s_set_status(rk_scmi_clock_t *clock, bool status)
2014 {
2015 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2),
2016 BITS_WITH_WMASK(!status, 0x1U, 14));
2017
2018 return 0;
2019 }
2020
clk_scmi_trng_s_get_rate(rk_scmi_clock_t * clock)2021 static unsigned long clk_scmi_trng_s_get_rate(rk_scmi_clock_t *clock)
2022 {
2023 return clk_scmi_hclk_secure_s_get_rate(clock);
2024 }
2025
clk_scmi_trng_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)2026 static int clk_scmi_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
2027 {
2028 return clk_scmi_hclk_secure_s_set_rate(clock, rate);
2029 }
2030
clk_scmi_trng_s_set_status(rk_scmi_clock_t * clock,bool status)2031 static int clk_scmi_trng_s_set_status(rk_scmi_clock_t *clock, bool status)
2032 {
2033 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3),
2034 BITS_WITH_WMASK(!status, 0x1U, 6));
2035
2036 return 0;
2037 }
2038
clk_scmi_h_trng_s_get_rate(rk_scmi_clock_t * clock)2039 static unsigned long clk_scmi_h_trng_s_get_rate(rk_scmi_clock_t *clock)
2040 {
2041 return clk_scmi_hclk_secure_s_get_rate(clock);
2042 }
2043
clk_scmi_h_trng_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)2044 static int clk_scmi_h_trng_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
2045 {
2046 return clk_scmi_hclk_secure_s_set_rate(clock, rate);
2047 }
2048
clk_scmi_h_trng_s_set_status(rk_scmi_clock_t * clock,bool status)2049 static int clk_scmi_h_trng_s_set_status(rk_scmi_clock_t *clock, bool status)
2050 {
2051 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2),
2052 BITS_WITH_WMASK(!status, 0x1U, 15));
2053
2054 return 0;
2055 }
2056
clk_scmi_p_otpc_s_get_rate(rk_scmi_clock_t * clock)2057 static unsigned long clk_scmi_p_otpc_s_get_rate(rk_scmi_clock_t *clock)
2058 {
2059 return clk_scmi_pclk_secure_s_get_rate(clock);
2060 }
2061
clk_scmi_p_otpc_s_set_rate(rk_scmi_clock_t * clock,unsigned long rate)2062 static int clk_scmi_p_otpc_s_set_rate(rk_scmi_clock_t *clock, unsigned long rate)
2063 {
2064 return clk_scmi_pclk_secure_s_set_rate(clock, rate);
2065 }
2066
clk_scmi_p_otpc_s_set_status(rk_scmi_clock_t * clock,bool status)2067 static int clk_scmi_p_otpc_s_set_status(rk_scmi_clock_t *clock, bool status)
2068 {
2069 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
2070 BITS_WITH_WMASK(!status, 0x1U, 13));
2071
2072 return 0;
2073 }
2074
clk_scmi_otpc_s_get_rate(rk_scmi_clock_t * clock)2075 static unsigned long clk_scmi_otpc_s_get_rate(rk_scmi_clock_t *clock)
2076 {
2077 return OSC_HZ;
2078 }
2079
clk_scmi_otpc_s_set_status(rk_scmi_clock_t * clock,bool status)2080 static int clk_scmi_otpc_s_set_status(rk_scmi_clock_t *clock, bool status)
2081 {
2082 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1),
2083 BITS_WITH_WMASK(!status, 0x1U, 14));
2084 return 0;
2085 }
2086
clk_scmi_otp_phy_get_rate(rk_scmi_clock_t * clock)2087 static unsigned long clk_scmi_otp_phy_get_rate(rk_scmi_clock_t *clock)
2088 {
2089 return OSC_HZ;
2090 }
2091
clk_scmi_otp_phy_set_status(rk_scmi_clock_t * clock,bool status)2092 static int clk_scmi_otp_phy_set_status(rk_scmi_clock_t *clock, bool status)
2093 {
2094 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18),
2095 BITS_WITH_WMASK(!status, 0x1U, 13));
2096 return 0;
2097 }
2098
clk_scmi_otpc_rd_get_rate(rk_scmi_clock_t * clock)2099 static unsigned long clk_scmi_otpc_rd_get_rate(rk_scmi_clock_t *clock)
2100 {
2101 return OSC_HZ;
2102 }
2103
clk_scmi_otpc_rd_set_status(rk_scmi_clock_t * clock,bool status)2104 static int clk_scmi_otpc_rd_set_status(rk_scmi_clock_t *clock, bool status)
2105 {
2106 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18),
2107 BITS_WITH_WMASK(!status, 0x1U, 12));
2108 return 0;
2109 }
2110
clk_scmi_otpc_arb_get_rate(rk_scmi_clock_t * clock)2111 static unsigned long clk_scmi_otpc_arb_get_rate(rk_scmi_clock_t *clock)
2112 {
2113 return OSC_HZ;
2114 }
2115
clk_scmi_otpc_arb_set_status(rk_scmi_clock_t * clock,bool status)2116 static int clk_scmi_otpc_arb_set_status(rk_scmi_clock_t *clock, bool status)
2117 {
2118 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18),
2119 BITS_WITH_WMASK(!status, 0x1U, 11));
2120 return 0;
2121 }
2122
2123 static const struct rk_clk_ops clk_scmi_cpul_ops = {
2124 .get_rate = clk_scmi_cpul_get_rate,
2125 .set_rate = clk_scmi_cpul_set_rate,
2126 .set_status = clk_scmi_cpul_set_status,
2127 };
2128
2129 static const struct rk_clk_ops clk_scmi_dsu_ops = {
2130 .get_rate = clk_scmi_dsu_get_rate,
2131 .set_rate = clk_scmi_dsu_set_rate,
2132 .set_status = clk_scmi_dsu_set_status,
2133 };
2134
2135 static const struct rk_clk_ops clk_scmi_cpub01_ops = {
2136 .get_rate = clk_scmi_cpub01_get_rate,
2137 .set_rate = clk_scmi_cpub01_set_rate,
2138 .set_status = clk_scmi_cpub01_set_status,
2139 };
2140
2141 static const struct rk_clk_ops clk_scmi_cpub23_ops = {
2142 .get_rate = clk_scmi_cpub23_get_rate,
2143 .set_rate = clk_scmi_cpub23_set_rate,
2144 .set_status = clk_scmi_cpub23_set_status,
2145 };
2146
2147 static const struct rk_clk_ops clk_scmi_gpu_ops = {
2148 .get_rate = clk_scmi_gpu_get_rate,
2149 .set_rate = clk_scmi_gpu_set_rate,
2150 .set_status = clk_scmi_gpu_set_status,
2151 };
2152
2153 static const struct rk_clk_ops clk_scmi_npu_ops = {
2154 .get_rate = clk_scmi_npu_get_rate,
2155 .set_rate = clk_scmi_npu_set_rate,
2156 .set_status = clk_scmi_npu_set_status,
2157 };
2158
2159 static const struct rk_clk_ops clk_scmi_sbus_ops = {
2160 .get_rate = clk_scmi_sbus_get_rate,
2161 .set_rate = clk_scmi_sbus_set_rate,
2162 .set_status = clk_scmi_sbus_set_status,
2163 };
2164
2165 static const struct rk_clk_ops clk_scmi_pclk_sbus_ops = {
2166 .get_rate = clk_scmi_pclk_sbus_get_rate,
2167 .set_rate = clk_scmi_pclk_sbus_set_rate,
2168 .set_status = clk_scmi_pclk_sbus_set_status,
2169 };
2170
2171 static const struct rk_clk_ops clk_scmi_cclk_sdmmc_ops = {
2172 .get_rate = clk_scmi_cclk_sdmmc_get_rate,
2173 .set_rate = clk_scmi_cclk_sdmmc_set_rate,
2174 .set_status = clk_scmi_cclk_sdmmc_set_status,
2175 };
2176
2177 static const struct rk_clk_ops clk_scmi_dclk_sdmmc_ops = {
2178 .get_rate = clk_scmi_dclk_sdmmc_get_rate,
2179 .set_rate = clk_scmi_dclk_sdmmc_set_rate,
2180 .set_status = clk_scmi_dclk_sdmmc_set_status,
2181 };
2182
2183 static const struct rk_clk_ops clk_scmi_aclk_secure_ns_ops = {
2184 .get_rate = clk_scmi_aclk_secure_ns_get_rate,
2185 .set_rate = clk_scmi_aclk_secure_ns_set_rate,
2186 .set_status = clk_scmi_aclk_secure_ns_set_status,
2187 };
2188
2189 static const struct rk_clk_ops clk_scmi_hclk_secure_ns_ops = {
2190 .get_rate = clk_scmi_hclk_secure_ns_get_rate,
2191 .set_rate = clk_scmi_hclk_secure_ns_set_rate,
2192 .set_status = clk_scmi_hclk_secure_ns_set_status,
2193 };
2194
2195 static const struct rk_clk_ops clk_scmi_tclk_wdt_ops = {
2196 .get_rate = clk_scmi_tclk_wdt_get_rate,
2197 .set_status = clk_scmi_tclk_wdt_set_status,
2198 };
2199
2200 static const struct rk_clk_ops clk_scmi_keyladder_core_ops = {
2201 .get_rate = clk_scmi_keyladder_core_get_rate,
2202 .set_rate = clk_scmi_keyladder_core_set_rate,
2203 .set_status = clk_scmi_keyladder_core_set_status,
2204 };
2205
2206 static const struct rk_clk_ops clk_scmi_keyladder_rng_ops = {
2207 .get_rate = clk_scmi_keyladder_rng_get_rate,
2208 .set_rate = clk_scmi_keyladder_rng_set_rate,
2209 .set_status = clk_scmi_keyladder_rng_set_status,
2210 };
2211
2212 static const struct rk_clk_ops clk_scmi_aclk_secure_s_ops = {
2213 .get_rate = clk_scmi_aclk_secure_s_get_rate,
2214 .set_rate = clk_scmi_aclk_secure_s_set_rate,
2215 .set_status = clk_scmi_aclk_secure_s_set_status,
2216 };
2217
2218 static const struct rk_clk_ops clk_scmi_hclk_secure_s_ops = {
2219 .get_rate = clk_scmi_hclk_secure_s_get_rate,
2220 .set_rate = clk_scmi_hclk_secure_s_set_rate,
2221 .set_status = clk_scmi_hclk_secure_s_set_status,
2222 };
2223
2224 static const struct rk_clk_ops clk_scmi_pclk_secure_s_ops = {
2225 .get_rate = clk_scmi_pclk_secure_s_get_rate,
2226 .set_rate = clk_scmi_pclk_secure_s_set_rate,
2227 .set_status = clk_scmi_pclk_secure_s_set_status,
2228 };
2229
2230 static const struct rk_clk_ops clk_scmi_crypto_rng_ops = {
2231 .get_rate = clk_scmi_crypto_rng_get_rate,
2232 .set_rate = clk_scmi_crypto_rng_set_rate,
2233 .set_status = clk_scmi_crypto_rng_set_status,
2234 };
2235
2236 static const struct rk_clk_ops clk_scmi_crypto_core_ops = {
2237 .get_rate = clk_scmi_crypto_core_get_rate,
2238 .set_rate = clk_scmi_crypto_core_set_rate,
2239 .set_status = clk_scmi_crypto_core_set_status,
2240 };
2241
2242 static const struct rk_clk_ops clk_scmi_crypto_pka_ops = {
2243 .get_rate = clk_scmi_crypto_pka_get_rate,
2244 .set_rate = clk_scmi_crypto_pka_set_rate,
2245 .set_status = clk_scmi_crypto_pka_set_status,
2246 };
2247
2248 static const struct rk_clk_ops clk_scmi_spll_ops = {
2249 .get_rate = clk_scmi_spll_get_rate,
2250 .set_rate = clk_scmi_spll_set_rate,
2251 .set_status = clk_scmi_spll_set_status,
2252 };
2253
2254 static const struct rk_clk_ops clk_scmi_hclk_sd_ops = {
2255 .get_rate = clk_scmi_hclk_sd_get_rate,
2256 .set_status = clk_scmi_hclk_sd_set_status,
2257 };
2258
2259 static const struct rk_clk_ops clk_scmi_crypto_rng_s_ops = {
2260 .get_rate = clk_scmi_crypto_rng_s_get_rate,
2261 .set_rate = clk_scmi_crypto_rng_s_set_rate,
2262 .set_status = clk_scmi_crypto_rng_s_set_status,
2263 };
2264
2265 static const struct rk_clk_ops clk_scmi_crypto_core_s_ops = {
2266 .get_rate = clk_scmi_crypto_core_s_get_rate,
2267 .set_rate = clk_scmi_crypto_core_s_set_rate,
2268 .set_status = clk_scmi_crypto_core_s_set_status,
2269 };
2270
2271 static const struct rk_clk_ops clk_scmi_crypto_pka_s_ops = {
2272 .get_rate = clk_scmi_crypto_pka_s_get_rate,
2273 .set_rate = clk_scmi_crypto_pka_s_set_rate,
2274 .set_status = clk_scmi_crypto_pka_s_set_status,
2275 };
2276
2277 static const struct rk_clk_ops clk_scmi_a_crypto_s_ops = {
2278 .get_rate = clk_scmi_a_crypto_s_get_rate,
2279 .set_rate = clk_scmi_a_crypto_s_set_rate,
2280 .set_status = clk_scmi_a_crypto_s_set_status,
2281 };
2282
2283 static const struct rk_clk_ops clk_scmi_h_crypto_s_ops = {
2284 .get_rate = clk_scmi_h_crypto_s_get_rate,
2285 .set_rate = clk_scmi_h_crypto_s_set_rate,
2286 .set_status = clk_scmi_h_crypto_s_set_status,
2287 };
2288
2289 static const struct rk_clk_ops clk_scmi_p_crypto_s_ops = {
2290 .get_rate = clk_scmi_p_crypto_s_get_rate,
2291 .set_rate = clk_scmi_p_crypto_s_set_rate,
2292 .set_status = clk_scmi_p_crypto_s_set_status,
2293 };
2294
2295 static const struct rk_clk_ops clk_scmi_a_keylad_s_ops = {
2296 .get_rate = clk_scmi_a_keylad_s_get_rate,
2297 .set_rate = clk_scmi_a_keylad_s_set_rate,
2298 .set_status = clk_scmi_a_keylad_s_set_status,
2299 };
2300
2301 static const struct rk_clk_ops clk_scmi_h_keylad_s_ops = {
2302 .get_rate = clk_scmi_h_keylad_s_get_rate,
2303 .set_rate = clk_scmi_h_keylad_s_set_rate,
2304 .set_status = clk_scmi_h_keylad_s_set_status,
2305 };
2306
2307 static const struct rk_clk_ops clk_scmi_p_keylad_s_ops = {
2308 .get_rate = clk_scmi_p_keylad_s_get_rate,
2309 .set_rate = clk_scmi_p_keylad_s_set_rate,
2310 .set_status = clk_scmi_p_keylad_s_set_status,
2311 };
2312
2313 static const struct rk_clk_ops clk_scmi_trng_s_ops = {
2314 .get_rate = clk_scmi_trng_s_get_rate,
2315 .set_rate = clk_scmi_trng_s_set_rate,
2316 .set_status = clk_scmi_trng_s_set_status,
2317 };
2318
2319 static const struct rk_clk_ops clk_scmi_h_trng_s_ops = {
2320 .get_rate = clk_scmi_h_trng_s_get_rate,
2321 .set_rate = clk_scmi_h_trng_s_set_rate,
2322 .set_status = clk_scmi_h_trng_s_set_status,
2323 };
2324
2325 static const struct rk_clk_ops clk_scmi_p_otpc_s_ops = {
2326 .get_rate = clk_scmi_p_otpc_s_get_rate,
2327 .set_rate = clk_scmi_p_otpc_s_set_rate,
2328 .set_status = clk_scmi_p_otpc_s_set_status,
2329 };
2330
2331 static const struct rk_clk_ops clk_scmi_otpc_s_ops = {
2332 .get_rate = clk_scmi_otpc_s_get_rate,
2333 .set_status = clk_scmi_otpc_s_set_status,
2334 };
2335
2336 static const struct rk_clk_ops clk_scmi_otp_phy_ops = {
2337 .get_rate = clk_scmi_otp_phy_get_rate,
2338 .set_status = clk_scmi_otp_phy_set_status,
2339 };
2340
2341 static const struct rk_clk_ops clk_scmi_otpc_rd_ops = {
2342 .get_rate = clk_scmi_otpc_rd_get_rate,
2343 .set_status = clk_scmi_otpc_rd_set_status,
2344 };
2345
2346 static const struct rk_clk_ops clk_scmi_otpc_arb_ops = {
2347 .get_rate = clk_scmi_otpc_arb_get_rate,
2348 .set_status = clk_scmi_otpc_arb_set_status,
2349 };
2350
2351 rk_scmi_clock_t clock_table[] = {
2352 RK3588_SCMI_CLOCK(SCMI_CLK_CPUL, "scmi_clk_cpul", &clk_scmi_cpul_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false),
2353 RK3588_SCMI_CLOCK(SCMI_CLK_DSU, "scmi_clk_dsu", &clk_scmi_dsu_ops, rk3588_cpul_rates, ARRAY_SIZE(rk3588_cpul_rates), false),
2354 RK3588_SCMI_CLOCK(SCMI_CLK_CPUB01, "scmi_clk_cpub01", &clk_scmi_cpub01_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false),
2355 RK3588_SCMI_CLOCK(SCMI_CLK_CPUB23, "scmi_clk_cpub23", &clk_scmi_cpub23_ops, rk3588_cpub_rates, ARRAY_SIZE(rk3588_cpub_rates), false),
2356 RK3588_SCMI_CLOCK(SCMI_CLK_DDR, "scmi_clk_ddr", NULL, NULL, 0, false),
2357 RK3588_SCMI_CLOCK(SCMI_CLK_GPU, "scmi_clk_gpu", &clk_scmi_gpu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false),
2358 RK3588_SCMI_CLOCK(SCMI_CLK_NPU, "scmi_clk_npu", &clk_scmi_npu_ops, rk3588_gpu_rates, ARRAY_SIZE(rk3588_gpu_rates), false),
2359 RK3588_SCMI_CLOCK(SCMI_CLK_SBUS, "scmi_clk_sbus", &clk_scmi_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2360 RK3588_SCMI_CLOCK(SCMI_PCLK_SBUS, "scmi_pclk_sbus", &clk_scmi_pclk_sbus_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2361 RK3588_SCMI_CLOCK(SCMI_CCLK_SD, "scmi_cclk_sd", &clk_scmi_cclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false),
2362 RK3588_SCMI_CLOCK(SCMI_DCLK_SD, "scmi_dclk_sd", &clk_scmi_dclk_sdmmc_ops, rk3588_sdmmc_rates, ARRAY_SIZE(rk3588_sdmmc_rates), false),
2363 RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_NS, "scmi_aclk_se_ns", &clk_scmi_aclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2364 RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_NS, "scmi_hclk_se_ns", &clk_scmi_hclk_secure_ns_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2365 RK3588_SCMI_CLOCK(SCMI_TCLK_WDT, "scmi_tclk_wdt", &clk_scmi_tclk_wdt_ops, NULL, 0, false),
2366 RK3588_SCMI_CLOCK(SCMI_KEYLADDER_CORE, "scmi_keylad_c", &clk_scmi_keyladder_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2367 RK3588_SCMI_CLOCK(SCMI_KEYLADDER_RNG, "scmi_keylad_r", &clk_scmi_keyladder_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2368 RK3588_SCMI_CLOCK(SCMI_ACLK_SECURE_S, "scmi_aclk_se_s", &clk_scmi_aclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2369 RK3588_SCMI_CLOCK(SCMI_HCLK_SECURE_S, "scmi_hclk_se_s", &clk_scmi_hclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2370 RK3588_SCMI_CLOCK(SCMI_PCLK_SECURE_S, "scmi_pclk_se_s", &clk_scmi_pclk_secure_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2371 RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG, "scmi_crypto_r", &clk_scmi_crypto_rng_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2372 RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE, "scmi_crypto_c", &clk_scmi_crypto_core_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2373 RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA, "scmi_crypto_p", &clk_scmi_crypto_pka_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2374 RK3588_SCMI_CLOCK(SCMI_SPLL, "scmi_spll", &clk_scmi_spll_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), false),
2375 RK3588_SCMI_CLOCK(SCMI_HCLK_SD, "scmi_hclk_sd", &clk_scmi_hclk_sd_ops, NULL, 0, false),
2376 RK3588_SCMI_CLOCK(SCMI_CRYPTO_RNG_S, "scmi_crypto_r_s", &clk_scmi_crypto_rng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2377 RK3588_SCMI_CLOCK(SCMI_CRYPTO_CORE_S, "scmi_crypto_c_s", &clk_scmi_crypto_core_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2378 RK3588_SCMI_CLOCK(SCMI_CRYPTO_PKA_S, "scmi_crypto_p_s", &clk_scmi_crypto_pka_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2379 RK3588_SCMI_CLOCK(SCMI_A_CRYPTO_S, "scmi_a_crypto_s", &clk_scmi_a_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2380 RK3588_SCMI_CLOCK(SCMI_H_CRYPTO_S, "scmi_h_crypto_s", &clk_scmi_h_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2381 RK3588_SCMI_CLOCK(SCMI_P_CRYPTO_S, "scmi_p_crypto_s", &clk_scmi_p_crypto_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2382 RK3588_SCMI_CLOCK(SCMI_A_KEYLADDER_S, "scmi_a_keylad_s", &clk_scmi_a_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2383 RK3588_SCMI_CLOCK(SCMI_H_KEYLADDER_S, "scmi_h_keylad_s", &clk_scmi_h_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2384 RK3588_SCMI_CLOCK(SCMI_P_KEYLADDER_S, "scmi_p_keylad_s", &clk_scmi_p_keylad_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2385 RK3588_SCMI_CLOCK(SCMI_TRNG_S, "scmi_trng_s", &clk_scmi_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2386 RK3588_SCMI_CLOCK(SCMI_H_TRNG_S, "scmi_h_trng_s", &clk_scmi_h_trng_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2387 RK3588_SCMI_CLOCK(SCMI_P_OTPC_S, "scmi_p_otpc_s", &clk_scmi_p_otpc_s_ops, rk3588_sbus_rates, ARRAY_SIZE(rk3588_sbus_rates), true),
2388 RK3588_SCMI_CLOCK(SCMI_OTPC_S, "scmi_otpc_s", &clk_scmi_otpc_s_ops, NULL, 0, true),
2389 RK3588_SCMI_CLOCK(SCMI_OTP_PHY, "scmi_otp_phy", &clk_scmi_otp_phy_ops, NULL, 0, false),
2390 RK3588_SCMI_CLOCK(SCMI_OTPC_AUTO_RD, "scmi_otpc_rd", &clk_scmi_otpc_rd_ops, NULL, 0, false),
2391 RK3588_SCMI_CLOCK(SCMI_OTPC_ARB, "scmi_otpc_arb", &clk_scmi_otpc_arb_ops, NULL, 0, false),
2392 };
2393
rockchip_scmi_clock_count(unsigned int agent_id __unused)2394 size_t rockchip_scmi_clock_count(unsigned int agent_id __unused)
2395 {
2396 return ARRAY_SIZE(clock_table);
2397 }
2398
rockchip_scmi_get_clock(uint32_t agent_id __unused,uint32_t clock_id)2399 rk_scmi_clock_t *rockchip_scmi_get_clock(uint32_t agent_id __unused,
2400 uint32_t clock_id)
2401 {
2402 rk_scmi_clock_t *table = NULL;
2403
2404 if (clock_id < ARRAY_SIZE(clock_table))
2405 table = &clock_table[clock_id];
2406
2407 if (table && !table->is_security)
2408 return table;
2409 else
2410 return NULL;
2411 }
2412
pvtplls_suspend(void)2413 void pvtplls_suspend(void)
2414 {
2415 clk_cpul_set_rate(408000000, PLL_SEL_NOR);
2416 clk_dsu_set_rate(408000000, PLL_SEL_NOR);
2417 clk_cpub01_set_rate(408000000, PLL_SEL_NOR);
2418 clk_cpub23_set_rate(408000000, PLL_SEL_NOR);
2419 }
2420
pvtplls_resume(void)2421 void pvtplls_resume(void)
2422 {
2423 clk_cpul_set_rate(sys_clk_info.cpul_rate, PLL_SEL_AUTO);
2424 clk_dsu_set_rate(sys_clk_info.dsu_rate, PLL_SEL_AUTO);
2425 clk_cpub01_set_rate(sys_clk_info.cpub01_rate, PLL_SEL_AUTO);
2426 clk_cpub23_set_rate(sys_clk_info.cpub23_rate, PLL_SEL_AUTO);
2427 }
2428
sys_reset_pvtplls_prepare(void)2429 void sys_reset_pvtplls_prepare(void)
2430 {
2431 clk_gpu_set_rate(100000000, PLL_SEL_NOR);
2432 clk_npu_set_rate(100000000, PLL_SEL_NOR);
2433 clk_cpul_set_rate(408000000, PLL_SEL_NOR);
2434 clk_cpub01_set_rate(408000000, PLL_SEL_NOR);
2435 clk_cpub23_set_rate(408000000, PLL_SEL_NOR);
2436 clk_dsu_set_rate(408000000, PLL_SEL_NOR);
2437 }
2438
rockchip_clock_init(void)2439 void rockchip_clock_init(void)
2440 {
2441 /* set gpll src div to 0 for cpul */
2442 mmio_write_32(DSUCRU_BASE + CRU_CLKSEL_CON(5), CLKDIV_5BITS_SHF(0U, 9));
2443 /* set gpll src div to 0 for cpub01 */
2444 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(0),
2445 CLKDIV_5BITS_SHF(0U, 1));
2446 /* set gpll src div to 0 for cpu23 */
2447 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(0),
2448 CLKDIV_5BITS_SHF(0U, 1));
2449
2450 mmio_write_32(BIGCORE0CRU_BASE + CRU_CLKSEL_CON(2),
2451 CPUB_PCLK_PATH_50M);
2452 mmio_write_32(BIGCORE1CRU_BASE + CRU_CLKSEL_CON(2),
2453 CPUB_PCLK_PATH_50M);
2454
2455 mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4),
2456 CLKDIV_5BITS_SHF(5U, 0));
2457 mmio_write_32(DSUCRU_BASE + DSUCRU_CLKSEL_CON(4),
2458 BITS_WITH_WMASK(PCLK_DSU_ROOT_SEL_GPLL,
2459 PCLK_DSU_ROOT_SEL_MASK,
2460 PCLK_DSU_ROOT_SEL_SHIFT));
2461
2462 sys_clk_info.cpul_table = rk3588_cpul_pvtpll_table;
2463 sys_clk_info.cpul_rate_count = ARRAY_SIZE(rk3588_cpul_pvtpll_table);
2464 sys_clk_info.cpub01_table = rk3588_cpub0_pvtpll_table;
2465 sys_clk_info.cpub01_rate_count = ARRAY_SIZE(rk3588_cpub0_pvtpll_table);
2466 sys_clk_info.cpub23_table = rk3588_cpub1_pvtpll_table;
2467 sys_clk_info.cpub23_rate_count = ARRAY_SIZE(rk3588_cpub1_pvtpll_table);
2468 memcpy(sys_clk_info.cpub23_table, sys_clk_info.cpub01_table,
2469 sys_clk_info.cpub01_rate_count * sizeof(*sys_clk_info.cpub01_table));
2470 sys_clk_info.gpu_table = rk3588_gpu_pvtpll_table;
2471 sys_clk_info.gpu_rate_count = ARRAY_SIZE(rk3588_gpu_pvtpll_table);
2472 sys_clk_info.npu_table = rk3588_npu_pvtpll_table;
2473 sys_clk_info.npu_rate_count = ARRAY_SIZE(rk3588_npu_pvtpll_table);
2474 }
2475