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/rk3399_ARM-atf/tools/cert_create/src/
H A Dmain.c93 int rem, i = 0; in print_help() local
124 printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); in print_help()
126 i++; in print_help()
133 int i; in get_key_alg() local
135 for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { in get_key_alg()
136 if (0 == strcmp(key_alg_str, key_algs_str[i])) { in get_key_alg()
137 return i; in get_key_alg()
158 int i; in get_hash_alg() local
160 for (i = 0 ; i < NUM_ELEM(hash_algs_str) ; i++) { in get_hash_alg()
161 if (0 == strcmp(hash_alg_str, hash_algs_str[i])) { in get_hash_alg()
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_pinmux.c225 uint32_t i; in config_pinmux() local
228 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) { in config_pinmux()
229 mmio_write_32(AGX5_PINMUX_PIN0SEL + hoff_ptr->pinmux_sel_array[i], in config_pinmux()
230 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
234 for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_io_array); i += 2) { in config_pinmux()
235 mmio_write_32(AGX5_PINMUX_IO0CTRL + hoff_ptr->pinmux_io_array[i], in config_pinmux()
236 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
245 for (i = 0; i < (ARRAY_SIZE(hoff_ptr->pinmux_fpga_array) - 4); i += 2) { in config_pinmux()
246 mmio_write_32(AGX5_PINMUX_EMAC0_USEFPGA + hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
247 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram.c17 uint32_t os_reg2_val, i; in dram_init() local
25 for (i = 0; i < 2; i++) { in dram_init()
26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init()
29 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) in dram_init()
32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); in dram_init()
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); in dram_init()
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); in dram_init()
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); in dram_init()
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); in dram_init()
[all …]
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm_helpers.c41 int i; in alloc_region_mem() local
47 for (i = 0; i < rgn_num; i++, r++) { in alloc_region_mem()
92 int i, j; in rockchip_reg_rgn_save() local
96 for (i = 0; i < rgn_num; i++) { in rockchip_reg_rgn_save()
97 r = &rgns[i]; in rockchip_reg_rgn_save()
112 int i, j; in rockchip_reg_rgn_restore() local
116 for (i = 0; i < rgn_num; i++) { in rockchip_reg_rgn_restore()
117 r = &rgns[i]; in rockchip_reg_rgn_restore()
134 int i, j; in rockchip_reg_rgn_restore_reverse() local
138 for (i = rgn_num - 1; i >= 0; i--) { in rockchip_reg_rgn_restore_reverse()
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/qos/M3N/
H A Dqos_init_m3n_v10.c150 uint32_t i; in qos_init_m3n_v10() local
152 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3n_v10()
153 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
154 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
156 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3n_v10()
157 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
158 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
161 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3n_v10()
162 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, in qos_init_m3n_v10()
163 qoswt_fix[i]); in qos_init_m3n_v10()
[all …]
/rk3399_ARM-atf/drivers/renesas/rzg/qos/G2N/
H A Dqos_init_g2n_v10.c148 uint32_t i; in qos_init_g2n_v10() local
150 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2n_v10()
151 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
152 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
154 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2n_v10()
155 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
156 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
159 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2n_v10()
160 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2n_v10()
161 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2n_v10()
[all …]
/rk3399_ARM-atf/drivers/arm/gicv5/
H A Dgicv5_main.c78 for (int i = 0U; i < num_regs; i++) { in iwb_enable() local
79 write_iwb_wenabler(base_addr, i, 0U); in iwb_enable()
83 for (int i = 0U; i < num_regs * 2; i++) { in iwb_enable() local
84 write_iwb_wdomainr(base_addr, i, 0x55555555); in iwb_enable()
87 for (uint32_t i = 0U; i < config->num_wires; i++) { in iwb_enable() local
88 assert(iwb_domain_supported(idr0, config->wires[i].domain)); in iwb_enable()
89 assert(config->wires[i].id <= num_regs * 32); in iwb_enable()
91 iwb_configure_domainr(base_addr, config->wires[i]); in iwb_enable()
92 iwb_configure_wtmr(base_addr, config->wires[i]); in iwb_enable()
125 for (uint32_t i = spi_base; i < spi_base + spi_range; i++) { in irs_enable() local
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c145 uint32_t i = 0; in clk_gate_con_save() local
147 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
148 slp_data.cru_gate_con[i] = in clk_gate_con_save()
149 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
154 uint32_t i; in clk_gate_con_disable() local
156 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_disable()
157 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
162 uint32_t i; in clk_gate_con_restore() local
164 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
165 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
[all …]
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dddrc.c57 uint32_t i; in bist() local
69 for (i = 0U; i < 4U; i++) { in bist()
70 csn_bnds[i] = ddr_in32(&ddr->bnds[i].a); in bist()
71 ddr_out32(&ddr->bnds[i].a, in bist()
72 (csn_bnds[i] & U(0xfffefffe)) >> 1U); in bist()
79 for (i = 0U; i < 36U; i++) { /* Go through all 37 */ in bist()
80 if ((i % 4U) == 0U) { in bist()
81 temp32 = ddr_in32(&ddr->dec[i >> 2U]); in bist()
83 shift = (3U - i % 4U) * 8U + 2U; in bist()
87 pos = i; in bist()
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/
H A Dxrdc_core.c188 unsigned int i, size; in xrdc_check_pd() local
202 for (i = 0U; i < size; i++) { in xrdc_check_pd()
203 if (item == list[i]) { in xrdc_check_pd()
229 unsigned int i, j; in xrdc_apply_config() local
232 for (i = 0U; i < ARRAY_SIZE(imx8ulp_mda); i++) { in xrdc_apply_config()
233 if (check_func(MDA_TYPE, imx8ulp_mda[i].mda_id)) { in xrdc_apply_config()
234 xrdc_config_mda(imx8ulp_mda[i].mda_id, in xrdc_apply_config()
235 imx8ulp_mda[i].did, imx8ulp_mda[i].sa); in xrdc_apply_config()
239 for (i = 0U; i < ARRAY_SIZE(imx8ulp_mrc); i++) { in xrdc_apply_config()
240 if (check_func(MRC_TYPE, imx8ulp_mrc[i].mrc_id)) { in xrdc_apply_config()
[all …]
/rk3399_ARM-atf/drivers/renesas/rza/ddr/
H A Dddr.c41 int i; in ddr_setup() local
88 for (i = 0; i < ARRAY_SIZE(swizzle_mc_tbl); i++) { in ddr_setup()
89 write_mc_reg(swizzle_mc_tbl[i][0], swizzle_mc_tbl[i][1]); in ddr_setup()
91 for (i = 0; i < ARRAY_SIZE(swizzle_phy_tbl); i++) { in ddr_setup()
92 write_phy_reg(swizzle_phy_tbl[i][0], swizzle_phy_tbl[i][1]); in ddr_setup()
144 int i; in program_mc1() local
147 for (i = 0; i < ARRAY_SIZE(mc_init_tbl); i++) { in program_mc1()
148 if (mc_init_tbl[i][0] == DDRMC_R006) { in program_mc1()
149 *lp_auto_entry_en = mc_init_tbl[i][1] & 0xF; in program_mc1()
151 mc_init_tbl[i][1] & 0xFFFFFFF0); in program_mc1()
[all …]
/rk3399_ARM-atf/drivers/marvell/
H A Dap807_clocks_init.c47 int i; in pll_set_freq() local
52 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in pll_set_freq()
54 mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val); in pll_set_freq()
58 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
61 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
65 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
74 int i; in aro_to_pll() local
76 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in aro_to_pll()
78 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
80 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); in aro_to_pll()
[all …]
/rk3399_ARM-atf/drivers/renesas/rzg/qos/G2M/
H A Dqos_init_g2m_v30.c104 uint32_t i; in qos_init_g2m_v30() local
161 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2m_v30()
162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v30()
165 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2m_v30()
166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v30()
170 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2m_v30()
171 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v30()
172 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v30()
[all …]
H A Dqos_init_g2m_v11.c104 uint32_t i; in qos_init_g2m_v11() local
160 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2m_v11()
161 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
162 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v11()
164 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2m_v11()
165 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
166 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v11()
169 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2m_v11()
170 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v11()
171 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2m_v11()
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/qos/H3/
H A Dqos_init_h3n_v30.c170 uint32_t i; in qos_init_h3n_v30() local
172 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3n_v30()
173 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3n_v30()
174 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3n_v30()
176 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3n_v30()
177 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3n_v30()
178 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3n_v30()
181 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_h3n_v30()
182 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, in qos_init_h3n_v30()
183 qoswt_fix[i]); in qos_init_h3n_v30()
[all …]
H A Dqos_init_h3_v30.c176 uint32_t i; in qos_init_h3_v30() local
178 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3_v30()
179 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3_v30()
180 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3_v30()
182 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3_v30()
183 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3_v30()
184 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3_v30()
187 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_h3_v30()
188 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, in qos_init_h3_v30()
189 qoswt_fix[i]); in qos_init_h3_v30()
[all …]
H A Dqos_init_h3_v20.c169 uint32_t i; in qos_init_h3_v20() local
171 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3_v20()
172 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3_v20()
173 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3_v20()
175 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3_v20()
176 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3_v20()
177 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3_v20()
180 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_h3_v20()
181 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, in qos_init_h3_v20()
182 qoswt_fix[i]); in qos_init_h3_v20()
[all …]
/rk3399_ARM-atf/drivers/renesas/rzg/qos/G2H/
H A Dqos_init_g2h_v30.c159 uint32_t i; in qos_init_g2h_v30() local
161 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2h_v30()
162 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2h_v30()
163 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2h_v30()
165 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2h_v30()
166 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2h_v30()
167 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2h_v30()
170 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2h_v30()
171 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2h_v30()
172 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2h_v30()
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/qos/M3/
H A Dqos_init_m3_v30.c161 uint32_t i; in qos_init_m3_v30() local
163 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3_v30()
164 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3_v30()
165 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3_v30()
167 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3_v30()
168 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3_v30()
169 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3_v30()
172 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3_v30()
173 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]); in qos_init_m3_v30()
174 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]); in qos_init_m3_v30()
[all …]
H A Dqos_init_m3_v11.c163 uint32_t i; in qos_init_m3_v11() local
165 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3_v11()
166 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
167 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
169 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3_v11()
170 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3_v11()
171 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3_v11()
174 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3_v11()
175 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]); in qos_init_m3_v11()
176 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]); in qos_init_m3_v11()
[all …]
/rk3399_ARM-atf/plat/arm/common/aarch64/
H A Darm_sdei.c29 uint32_t i; in plat_sdei_setup() local
33 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_cnt); i++) { in plat_sdei_setup()
34 arm_sdei_private[i + 1] = (sdei_ev_map_t)SDEI_PRIVATE_EVENT( in plat_sdei_setup()
35 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_nums[i]), in plat_sdei_setup()
36 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_intrs[i]), in plat_sdei_setup()
37 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_flags[i])); in plat_sdei_setup()
40 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_cnt); i++) { in plat_sdei_setup()
41 arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT( in plat_sdei_setup()
42 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_nums[i]), in plat_sdei_setup()
43 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_intrs[i]), in plat_sdei_setup()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Ddram.c100 unsigned int i, fsp_index; in get_mr_values() local
103 for (i = 0U; i < 4U; i++) { in get_mr_values()
104 init_val = mmio_read_32(fsp_init_reg[fsp_index][i]); in get_mr_values()
105 mr_value[fsp_index][2*i] = init_val >> 16; in get_mr_values()
106 mr_value[fsp_index][2*i + 1] = init_val & 0xFFFF; in get_mr_values()
120 uint32_t i, offset; in save_rank_setting() local
126 for (i = 0U; i < pstate_num; i++) { in save_rank_setting()
127 offset = i ? (i + 1) * 0x1000 : 0U; in save_rank_setting()
128 dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset); in save_rank_setting()
130 dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset); in save_rank_setting()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/src/
H A Dthermal_lvts.c135 unsigned int i; in lvts_thermal_check_all_sensing_point_idle() local
142 for (i = 0; i < lvts_data->num_tc; i++) { in lvts_thermal_check_all_sensing_point_idle()
143 if (tc[i].ctrl_on_off == CTRL_OFF) in lvts_thermal_check_all_sensing_point_idle()
146 base = GET_BASE_ADDR(lvts_data, i); in lvts_thermal_check_all_sensing_point_idle()
150 error_code = (i << HALF_WORD) in lvts_thermal_check_all_sensing_point_idle()
167 unsigned int i; in wait_all_tc_sensing_point_idle() local
189 for (i = 0; i < lvts_data->num_tc; i++) { in wait_all_tc_sensing_point_idle()
190 if (tc[i].ctrl_on_off == CTRL_OFF) in wait_all_tc_sensing_point_idle()
193 base = GET_BASE_ADDR(lvts_data, i); in wait_all_tc_sensing_point_idle()
211 i, error_code); in wait_all_tc_sensing_point_idle()
[all …]
/rk3399_ARM-atf/plat/nuvoton/npcm845x/
H A Dnpcm845x_psci.c168 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend() local
170 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_suspend()
188 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_on_finish() local
190 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_on_finish()
210 for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) { in npcm845x_pwr_domain_suspend_finish() local
212 __func__, i, target_state->pwr_domain_state[i]); in npcm845x_pwr_domain_suspend_finish()
259 int i; in npcm845x_validate_power_state() local
269 for (i = 0; !!npcm845x_pm_idle_states[i]; i++) { in npcm845x_validate_power_state()
270 if (power_state == npcm845x_pm_idle_states[i]) { in npcm845x_validate_power_state()
276 if (!npcm845x_pm_idle_states[i]) { in npcm845x_validate_power_state()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600_multichip.c29 unsigned int i; in gic600_multichip_gicd_base_for_spi() local
32 for (i = 0U; i < GIC600_MAX_MULTICHIP; i++) { in gic600_multichip_gicd_base_for_spi()
33 if ((spi_id <= plat_gic_multichip_data->spi_ids[i].spi_id_max) && in gic600_multichip_gicd_base_for_spi()
34 (spi_id >= plat_gic_multichip_data->spi_ids[i].spi_id_min)) { in gic600_multichip_gicd_base_for_spi()
40 assert(i < GIC600_MAX_MULTICHIP); in gic600_multichip_gicd_base_for_spi()
42 return plat_gic_multichip_data->spi_ids[i].gicd_base; in gic600_multichip_gicd_base_for_spi()
205 unsigned int i, spi_id_min, spi_id_max, blocks_of_32; in gic600_multichip_validate_data() local
216 for (i = 0U; i < multichip_data->chip_count; i++) { in gic600_multichip_validate_data()
217 spi_id_min = multichip_data->spi_ids[i].spi_id_min; in gic600_multichip_validate_data()
218 spi_id_max = multichip_data->spi_ids[i].spi_id_max; in gic600_multichip_validate_data()
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