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| H A D | RK3308MINIALL.ini | fe30ebb9b84fb15f814abec065f25ec819472902 Fri Apr 13 13:02:42 UTC 2018 Zhihuan He <huan.he@rock-chips.com> rk3308: ddr: add initial version v1.11
from commit :
7b62dfc rk3308: DDR Version V1.11
add
1.set vpll0 in 1179.648MHz,vpll1 in 903.168MHz
2.ddr in vpll0,set 589MHz
3.adjusted deskew for aligning DQS and CK
4.delete clk 50% duty ratio setting in cru
5.set APLL,DPLL,VPLL0,VPLL1 without level shift
6.set pll vco high,but lower 3.2GHz,for minimum jitter.
7.add ddr scramble,include enable pmu pvtm.
8.updata ddr config grf_os_reg2,grf_os_reg3 to v1.08.
Change-Id: Ia459f53d7d9623f3af7e0de1edc2f99735d57c80
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
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