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H A Dsub.mkfdb66914582775682f64cbe018dad058b9a61643 Mon Dec 19 10:25:20 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap handling, including syscalls handling.
- Thread allocation, execution, suspension, freeing with slight changes
to set RISC-V registers such as CSRs.
- RPC.

Pending routines:
- Floatting point support F/D/Q/L extensions and software FP.
- Abort mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
H A Dthread_arch.cfdb66914582775682f64cbe018dad058b9a61643 Mon Dec 19 10:25:20 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: implement thread management routines in thread_arch.c

This commit implements an initial thread management for RISC-V. It covers
the following routines:

- Exceptions un/masking
- Trap handling, including syscalls handling.
- Thread allocation, execution, suspension, freeing with slight changes
to set RISC-V registers such as CSRs.
- RPC.

Pending routines:
- Floatting point support F/D/Q/L extensions and software FP.
- Abort mode.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>