Searched hist:fd1dd4cb2c88f64a411c8482007e4669a563b80d (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | arch_features.h | fd1dd4cb2c88f64a411c8482007e4669a563b80d Wed Jan 25 12:26:14 UTC 2023 Andre Przywara <andre.przywara@arm.com> refactor(cpufeat): wrap CPU ID register field isolation
Some MISRA test complains about our code to isolate CPU ID register
fields: the ID registers (and associated masks) are 64 bits wide, but
the eventual field is always 4 bits wide only, so we use an unsigned
int to represent that. MISRA dislikes the differing width here.
Since the code to extract a feature field from a CPU ID register is very
schematic already, provide a wrapper macro to make this more readable,
and do the proper casting in one central place on the way.
While at it, use the same macro for the AArch32 feature detection side.
Change-Id: Ie102a9e7007a386f5879ec65e159ff041504a4ee
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch_features.h | fd1dd4cb2c88f64a411c8482007e4669a563b80d Wed Jan 25 12:26:14 UTC 2023 Andre Przywara <andre.przywara@arm.com> refactor(cpufeat): wrap CPU ID register field isolation
Some MISRA test complains about our code to isolate CPU ID register
fields: the ID registers (and associated masks) are 64 bits wide, but
the eventual field is always 4 bits wide only, so we use an unsigned
int to represent that. MISRA dislikes the differing width here.
Since the code to extract a feature field from a CPU ID register is very
schematic already, provide a wrapper macro to make this more readable,
and do the proper casting in one central place on the way.
While at it, use the same macro for the AArch32 feature detection side.
Change-Id: Ie102a9e7007a386f5879ec65e159ff041504a4ee
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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