Searched hist:fad7d735a001a542a2aae60cb1a68a70a4bb0245 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/board/freescale/mx6sxsabresd/ |
| H A D | mx6sxsabresd.c | fad7d735a001a542a2aae60cb1a68a70a4bb0245 Wed Dec 31 03:01:40 UTC 2014 Peng Fan <Peng.Fan@freescale.com> imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.
Add QSPI related macro in configuration header file.
Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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| /rk3399_rockchip-uboot/include/configs/ |
| H A D | mx6sxsabresd.h | fad7d735a001a542a2aae60cb1a68a70a4bb0245 Wed Dec 31 03:01:40 UTC 2014 Peng Fan <Peng.Fan@freescale.com> imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.
Add QSPI related macro in configuration header file.
Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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