| /rk3399_rockchip-uboot/arch/arm/include/asm/proc-armv/ |
| H A D | ptrace.h | faa7eb0f76fd6e206963e74af89afc949c2e2c17 Fri Jul 13 03:55:22 UTC 2018 Joseph Chen <chenjh@rock-chips.com> armv8: exceptions: optimize exception regs info
Add arm core registers bits description, it looks like:
Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 000000000025def4
* SP = 0000000039d4a6b0
* ESR_EL2 = 0000000040732550
EC[31:26] == 001100, Exception from an MCRR or MRRC access
IL[25] == 0, 16-bit instruction trapped
* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
* SPSR_EL2 = 0000000080000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h
* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled
* VBAR_EL2 = 000000003dd55800
* HCR_EL2 = 000000000800003a
* TTBR0_EL2 = 000000003fff0000
x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910
Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/ |
| H A D | exceptions.S | faa7eb0f76fd6e206963e74af89afc949c2e2c17 Fri Jul 13 03:55:22 UTC 2018 Joseph Chen <chenjh@rock-chips.com> armv8: exceptions: optimize exception regs info
Add arm core registers bits description, it looks like:
Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 000000000025def4
* SP = 0000000039d4a6b0
* ESR_EL2 = 0000000040732550
EC[31:26] == 001100, Exception from an MCRR or MRRC access
IL[25] == 0, 16-bit instruction trapped
* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
* SPSR_EL2 = 0000000080000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h
* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled
* VBAR_EL2 = 000000003dd55800
* HCR_EL2 = 000000000800003a
* TTBR0_EL2 = 000000003fff0000
x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910
Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
|
| /rk3399_rockchip-uboot/arch/arm/lib/ |
| H A D | interrupts_64.c | faa7eb0f76fd6e206963e74af89afc949c2e2c17 Fri Jul 13 03:55:22 UTC 2018 Joseph Chen <chenjh@rock-chips.com> armv8: exceptions: optimize exception regs info
Add arm core registers bits description, it looks like:
Relocate offset = 000000003db55000
* ELR(PC) = 000000000025bd78
* LR = 000000000025def4
* SP = 0000000039d4a6b0
* ESR_EL2 = 0000000040732550
EC[31:26] == 001100, Exception from an MCRR or MRRC access
IL[25] == 0, 16-bit instruction trapped
* DAIF = 00000000000003c0
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 1, IRQ masked
F[6] == 1, FIQ masked
* SPSR_EL2 = 0000000080000349
D[9] == 1, DBG masked
A[8] == 1, ABORT masked
I[7] == 0, IRQ not masked
F[6] == 1, FIQ masked
M[4] == 0, Exception taken from AArch64
M[3:0] == 1001, EL2h
* SCTLR_EL2 = 0000000030c51835
I[12] == 1, Icaches enabled
C[2] == 1, Dcache enabled
M[0] == 1, MMU enabled
* VBAR_EL2 = 000000003dd55800
* HCR_EL2 = 000000000800003a
* TTBR0_EL2 = 000000003fff0000
x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910
Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
|