Searched hist:f68d3063491442ca5d871d3019a9d3f195873ed7 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet_serdes.c | f68d3063491442ca5d871d3019a9d3f195873ed7 Thu Apr 14 20:37:06 UTC 2011 Timur Tabi <timur@freescale.com> powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA
Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The
current code does this only for XAUI, so extend it to the other protocols.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | immap_85xx.h | f68d3063491442ca5d871d3019a9d3f195873ed7 Thu Apr 14 20:37:06 UTC 2011 Timur Tabi <timur@freescale.com> powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA
Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The
current code does this only for XAUI, so extend it to the other protocols.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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