Searched hist:f4b54213e855ff3b67f052923fab966614797036 (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/include/drivers/ |
| H A D | imsic.h | f4b54213e855ff3b67f052923fab966614797036 Thu Feb 27 07:26:50 UTC 2025 Huang Borong <huangborong@bosc.ac.cn> drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).
This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.
Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/drivers/ |
| H A D | imsic.c | f4b54213e855ff3b67f052923fab966614797036 Thu Feb 27 07:26:50 UTC 2025 Huang Borong <huangborong@bosc.ac.cn> drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).
This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.
Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| H A D | sub.mk | f4b54213e855ff3b67f052923fab966614797036 Thu Feb 27 07:26:50 UTC 2025 Huang Borong <huangborong@bosc.ac.cn> drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).
This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.
Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/arch/riscv/include/ |
| H A D | riscv.h | f4b54213e855ff3b67f052923fab966614797036 Thu Feb 27 07:26:50 UTC 2025 Huang Borong <huangborong@bosc.ac.cn> drivers: add RISC-V IMSIC interrupt driver
The RISC-V Advanced Interrupt Architecture (AIA) specification introduces
the IMSIC as a new external interrupt controller. An IMSIC receives and
records incoming message-signaled interrupts (MSIs).
This commit enables the initialization of the IMSIC based on the device
tree and adds control and status registers (CSRs) for indirect access to
the IMSIC as well as for reading interrupt identities.
Use the `CFG_RISCV_IMSIC` flag to control whether to build this driver.
For more details, see: https://github.com/riscv/riscv-aia
Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|