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/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.cf4aaa9fd6e6b4edd03976680b94e1c24aa582a68 Mon Sep 25 14:30:34 UTC 2023 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update DDR range checking for Agilex5

Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>