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/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_speed.cf3acaf438de74a0b278abc71fb2aca7e7aa86ffa Sun Jun 12 06:42:04 UTC 2016 Hou Zhiqiang <Zhiqiang.Hou@nxp.com> armv8/fsl_lsch2: Correct the cores frequency initialization

The register CLKCNCSR controls the frequency of all cores in the same
cluster.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>