Searched hist:f30ea7ca3b78e06fcc844f828bd21faf29166521 (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/riscv/include/ |
| H A D | sub.mk | f30ea7ca3b78e06fcc844f828bd21faf29166521 Fri Jul 01 09:15:23 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: define RISC-V instruction set architecture in encoding.h
Define standard RISC-V instruction opcodes, control and status registers.
This file is auto-generated from riscv-opcodes and it is subject of
regular updates.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
|
| H A D | encoding.h | f30ea7ca3b78e06fcc844f828bd21faf29166521 Fri Jul 01 09:15:23 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: define RISC-V instruction set architecture in encoding.h
Define standard RISC-V instruction opcodes, control and status registers.
This file is auto-generated from riscv-opcodes and it is subject of
regular updates.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
|
| /optee_os/scripts/ |
| H A D | checkpatch_inc.sh | f30ea7ca3b78e06fcc844f828bd21faf29166521 Fri Jul 01 09:15:23 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: define RISC-V instruction set architecture in encoding.h
Define standard RISC-V instruction opcodes, control and status registers.
This file is auto-generated from riscv-opcodes and it is subject of
regular updates.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
|