Searched hist:f2dec49b7aeacd4cf36cacecc2a62ca925800e7a (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/arm/include/sm/ |
| H A D | sm.h | f2dec49b7aeacd4cf36cacecc2a62ca925800e7a Thu Mar 10 10:10:14 UTC 2016 Jens Wiklander <jens.wiklander@linaro.org> arm: sm: [bugfix] save/restore fiq core registers
Currently there's a security problem with the FIQ registers for armv7
targets, both with leaking information and that normal world can change
stack pointer for FIQ mode. This patch fixes this problem.
Saves and restores FIQ core registers (spsr, sp, lr) when switching
secre/non-secure state.
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (modified QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| /optee_os/core/arch/arm/sm/ |
| H A D | sm_a32.S | f2dec49b7aeacd4cf36cacecc2a62ca925800e7a Thu Mar 10 10:10:14 UTC 2016 Jens Wiklander <jens.wiklander@linaro.org> arm: sm: [bugfix] save/restore fiq core registers
Currently there's a security problem with the FIQ registers for armv7
targets, both with leaking information and that normal world can change
stack pointer for FIQ mode. This patch fixes this problem.
Saves and restores FIQ core registers (spsr, sp, lr) when switching
secre/non-secure state.
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (modified QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/kernel/ |
| H A D | thread_a32.S | f2dec49b7aeacd4cf36cacecc2a62ca925800e7a Thu Mar 10 10:10:14 UTC 2016 Jens Wiklander <jens.wiklander@linaro.org> arm: sm: [bugfix] save/restore fiq core registers
Currently there's a security problem with the FIQ registers for armv7
targets, both with leaking information and that normal world can change
stack pointer for FIQ mode. This patch fixes this problem.
Saves and restores FIQ core registers (spsr, sp, lr) when switching
secre/non-secure state.
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (modified QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|