Searched hist:ef87cab66492fe530bb6ec2e499b030c5ae60286 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | interactive.c | ef87cab66492fe530bb6ec2e499b030c5ae60286 Fri Sep 05 05:52:43 UTC 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | ctrl_regs.c | ef87cab66492fe530bb6ec2e499b030c5ae60286 Fri Sep 05 05:52:43 UTC 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/include/ |
| H A D | fsl_ddr_sdram.h | ef87cab66492fe530bb6ec2e499b030c5ae60286 Fri Sep 05 05:52:43 UTC 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
|