Searched hist:ef00a9232c4876b70c6aec88be33e6977303796b (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/riscv/include/kernel/ |
| H A D | thread_private_arch.h | ef00a9232c4876b70c6aec88be33e6977303796b Wed Jul 24 14:37:07 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Rename and re-order parameters of the interrupt handlers
Rename thread_interrupt_handler() to thread_native_interrupt_handler(),
since we are going to support the foreign interrupt handler.
The native interrupts are handled in OP-TEE side, while the foreign
interrupts are handled outside OP-TEE.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| /optee_os/core/arch/riscv/kernel/ |
| H A D | thread_arch.c | ef00a9232c4876b70c6aec88be33e6977303796b Wed Jul 24 14:37:07 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Rename and re-order parameters of the interrupt handlers
Rename thread_interrupt_handler() to thread_native_interrupt_handler(),
since we are going to support the foreign interrupt handler.
The native interrupts are handled in OP-TEE side, while the foreign
interrupts are handled outside OP-TEE.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | thread_rv.S | ef00a9232c4876b70c6aec88be33e6977303796b Wed Jul 24 14:37:07 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Rename and re-order parameters of the interrupt handlers
Rename thread_interrupt_handler() to thread_native_interrupt_handler(),
since we are going to support the foreign interrupt handler.
The native interrupts are handled in OP-TEE side, while the foreign
interrupts are handled outside OP-TEE.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|