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| H A D | thread_arch.c | ed89e93936ee05335feda2f22246bf75070792e8 Wed Oct 11 16:00:24 UTC 2023 Alvin Chang <alvinga@andestech.com> core: riscv: Fix logic of thread_{get/set}_exceptions()
In ARM, the bits in DAIF register are used to mask the interrupts. While
in RISC-V, the bits in CSR XIE are used to enable(unmask) corresponding
interrupt sources.
To not modify the function of thread_get_exceptions(), we invert the
bits after reading the value of CSR XIE, as mask.
To not modify the function of thread_set_exceptions(), we invert the
bits in given "exceptions" before writing "exceptions" into CSR
XIE. Therefore, the intended masked exception bits will be cleared
when we write the final value into CSR XIE to mask those interrupts.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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