Searched hist:eadb6be0abd1c85df3c63609f0727d22e48ecc83 (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/include/ |
| H A D | encoding.h | eadb6be0abd1c85df3c63609f0727d22e48ecc83 Wed Jul 17 08:43:51 UTC 2024 Yu Chien Peter Lin <peterlin@andestech.com> core: riscv: core_mmu_arch: fix PPN field extraction from PTE
The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits, thus PPN field should be masked out with PTE_PPN.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| /optee_os/core/arch/riscv/mm/ |
| H A D | core_mmu_arch.c | eadb6be0abd1c85df3c63609f0727d22e48ecc83 Wed Jul 17 08:43:51 UTC 2024 Yu Chien Peter Lin <peterlin@andestech.com> core: riscv: core_mmu_arch: fix PPN field extraction from PTE
The upper bits of page table entry may contain other fields
introduced since Priv. ISA spec. v1.11 (20211203), such as PBMT
and N bits, thus PPN field should be masked out with PTE_PPN.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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