Searched hist:e497421d7f1e13d15313d1ca71a8e91f370cce1e (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/versal/include/ |
| H A D | plat_private.h | e497421d7f1e13d15313d1ca71a8e91f370cce1e Fri Aug 26 22:06:00 UTC 2022 Tanmay Shah <tanmay.shah@amd.com> feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
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| H A D | versal_def.h | e497421d7f1e13d15313d1ca71a8e91f370cce1e Fri Aug 26 22:06:00 UTC 2022 Tanmay Shah <tanmay.shah@amd.com> feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
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| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | bl31_versal_setup.c | e497421d7f1e13d15313d1ca71a8e91f370cce1e Fri Aug 26 22:06:00 UTC 2022 Tanmay Shah <tanmay.shah@amd.com> feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
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