Searched hist:e27f2dd721d8121177cb32a63684557fa625d4bf (Results 1 – 1 of 1) sorted by relevance
| /rk3399_rockchip-uboot/board/ti/am43xx/ |
| H A D | board.c | e27f2dd721d8121177cb32a63684557fa625d4bf Tue Feb 18 12:31:57 UTC 2014 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM4372: Update EMIF registers for DDR3
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|