Searched hist:e26b8e0f3e4c3eb55afa215a9da60478fa4fa4ac (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/drivers/ |
| H A D | stm32_ipcc.c | e26b8e0f3e4c3eb55afa215a9da60478fa4fa4ac Wed Mar 27 15:33:55 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> drivers: add IPCC driver and its RIF support
This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restrictions and that the IPCC has dedicated RIF configuration
registers.
RIF configuration data is part of the ipcc_pdata structure.
CID filtering is applied to the entirety of the channels of a processor.
When CID filtering is enabled for a processor, it enables the filtering and
the IPCC interrupt routing for all of its IPCC channels.
However, security and privilege configuration granularity go as far as
configuration for each IPCC channel.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| H A D | sub.mk | e26b8e0f3e4c3eb55afa215a9da60478fa4fa4ac Wed Mar 27 15:33:55 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> drivers: add IPCC driver and its RIF support
This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restrictions and that the IPCC has dedicated RIF configuration
registers.
RIF configuration data is part of the ipcc_pdata structure.
CID filtering is applied to the entirety of the channels of a processor.
When CID filtering is enabled for a processor, it enables the filtering and
the IPCC interrupt routing for all of its IPCC channels.
However, security and privilege configuration granularity go as far as
configuration for each IPCC channel.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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