Searched hist:dfa05b243a440d4b412cbd80678162621c576aed (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | thread_arch.c | dfa05b243a440d4b412cbd80678162621c576aed Mon Sep 09 05:42:25 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Set exception return PC into XEPC for entering user mode
Instead of setting exception return PC into "ra" register and assign it
to XEPC, we should directly set exception return PC into "XEPC" CSR to
improve code redability.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
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| H A D | thread_rv.S | dfa05b243a440d4b412cbd80678162621c576aed Mon Sep 09 05:42:25 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Set exception return PC into XEPC for entering user mode
Instead of setting exception return PC into "ra" register and assign it
to XEPC, we should directly set exception return PC into "XEPC" CSR to
improve code redability.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
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