Searched hist:dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/mips/lib/ |
| H A D | cache_init.S | dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e Thu Jan 29 01:28:02 UTC 2015 Paul Burton <paul.burton@imgtec.com> MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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| /rk3399_rockchip-uboot/arch/mips/ |
| H A D | Kconfig | dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e Thu Jan 29 01:28:02 UTC 2015 Paul Burton <paul.burton@imgtec.com> MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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