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| H A D | tlb.c | dd332e18d082de75eca3fc2c7c778f5d4571a096 Thu Nov 13 17:08:57 UTC 2008 Anatolij Gustschin <agust@denx.de> 85xx: socrates: fix DDR SDRAM tlb entry configuration
since commit be0bd8234b9777ecd63c4c686f72af070d886517
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:
socrates>l2cam 7 9
IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS
7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX
8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX
9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX
This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
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