Searched hist:db891f32f6c2100beb6c7d8eedcab2df57df632f (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/ |
| H A D | plat_setup.c | db891f32f6c2100beb6c7d8eedcab2df57df632f Fri Mar 23 17:44:40 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.
This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.
Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| H A D | plat_psci_handlers.c | db891f32f6c2100beb6c7d8eedcab2df57df632f Fri Mar 23 17:44:40 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms
Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.
This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.
Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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