Home
last modified time | relevance | path

Searched hist:da91cfed54ec44d88f93af2adfbdeada8ab4403e (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dvirt-v7.cda91cfed54ec44d88f93af2adfbdeada8ab4403e Wed Aug 03 20:08:55 UTC 2016 Stefan Agner <stefan.agner@toradex.com> ARM: non-sec: flush code cacheline aligned

Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>