Searched hist:d90fdba6ca0b08c77cced6e914609e3696dd5909 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet_serdes.c | d90fdba6ca0b08c77cced6e914609e3696dd5909 Mon Apr 18 22:16:00 UTC 2011 Timur Tabi <timur@freescale.com> powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.
Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly. The
work-around is to enable and then disable bank two after bank three is
enabled.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | config_mpc85xx.h | d90fdba6ca0b08c77cced6e914609e3696dd5909 Mon Apr 18 22:16:00 UTC 2011 Timur Tabi <timur@freescale.com> powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.
Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly. The
work-around is to enable and then disable bank two after bank three is
enabled.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|