Home
last modified time | relevance | path

Searched hist:d608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.Sd608254b0aa23607df1dcb5a7ca07de9a8ec9bb0 Wed Sep 21 10:18:58 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: Clear hazard between TagLo writes & cache ops

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>