Home
last modified time | relevance | path

Searched hist:d5ce3574619d6814ea095a798702e342d45203d4 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/aspeed/
H A Dclk_ast2500.cd5ce3574619d6814ea095a798702e342d45203d4 Mon Jan 30 19:35:04 UTC 2017 maxims@google.com <maxims@google.com> aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>