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| H A D | designware_spi.c | cccfaa061588768f9ca8c90b9c8cbebf4297e225 Thu Mar 22 10:50:43 UTC 2018 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> UPSTREAM: DW SPI: fix tx data loss on FIFO flush
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)
So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.
Change-Id: I13be86b6b7da544ff64656fdb62ea79d5ee16d26
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c6b4f031d96a4e1d59761b294829b058b098f3df)
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