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H A Dentry.Sca71b6fa3fb3feb0282b04f91b27eab518118ac8 Sat Mar 15 10:09:09 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>