Searched hist:c98d80112d6d52b3a8b2ab403232b5265c13046b (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | asm-defines.c | c98d80112d6d52b3a8b2ab403232b5265c13046b Sat Mar 15 13:42:10 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: refactor MMU enablement code
Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identity mapped section to maintain
execution continuity during the VA->PA transition. It adjusts
the stack pointer, global pointer, thread pointer and ra register
with the ASLR offset.
The console is reinitialized after ASLR mapping is active since
the registered addresses need to be updated.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
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| H A D | entry.S | c98d80112d6d52b3a8b2ab403232b5265c13046b Sat Mar 15 13:42:10 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: refactor MMU enablement code
Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identity mapped section to maintain
execution continuity during the VA->PA transition. It adjusts
the stack pointer, global pointer, thread pointer and ra register
with the ASLR offset.
The console is reinitialized after ASLR mapping is active since
the registered addresses need to be updated.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
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