Searched hist:c7cf29335a7346b75ae8237a3ac2b08af98b8ea5 (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/include/drivers/ |
| H A D | stpmic1.h | c7cf29335a7346b75ae8237a3ac2b08af98b8ea5 Mon May 06 09:30:28 UTC 2019 Etienne Carriere <etienne.carriere@st.com> core: introduce STPMIC1 driver
STPMIC1 is a power management chip for the stm32mp1 platform. It is
accessed through an I2C bus. STPMIC1 provides regulators and other
features as interrupt sources and watchdogs.
STPMIC1 configuration is expected from a secure device tree blob, that
currently is the embedded DTB.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| /optee_os/core/drivers/ |
| H A D | stpmic1.c | c7cf29335a7346b75ae8237a3ac2b08af98b8ea5 Mon May 06 09:30:28 UTC 2019 Etienne Carriere <etienne.carriere@st.com> core: introduce STPMIC1 driver
STPMIC1 is a power management chip for the stm32mp1 platform. It is
accessed through an I2C bus. STPMIC1 provides regulators and other
features as interrupt sources and watchdogs.
STPMIC1 configuration is expected from a secure device tree blob, that
currently is the embedded DTB.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | sub.mk | c7cf29335a7346b75ae8237a3ac2b08af98b8ea5 Mon May 06 09:30:28 UTC 2019 Etienne Carriere <etienne.carriere@st.com> core: introduce STPMIC1 driver
STPMIC1 is a power management chip for the stm32mp1 platform. It is
accessed through an I2C bus. STPMIC1 provides regulators and other
features as interrupt sources and watchdogs.
STPMIC1 configuration is expected from a secure device tree blob, that
currently is the embedded DTB.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|