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H A Dgen_ldelf_hex.pyc706c2449b50bbfa62528ee515a7ac07fec98769 Tue Apr 21 13:04:34 UTC 2020 Jerome Forissier <jerome@forissier.org> scripts/gen_ldelf_hex.py: relax rules for PT_LOAD segments

Latest Clang [1] generates the following ldelf.elf:

Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x00000000 0x00000000 0x04834 0x04834 R E 0x1000
LOAD 0x005838 0x00004838 0x00004838 0x01620 0x01620 R 0x1000
LOAD 0x007000 0x00006000 0x00006000 0x0006c 0x0006c RW 0x1000
LOAD 0x00706c 0x0000606c 0x0000606c 0x00068 0x00078 RW 0x1000
DYNAMIC 0x007000 0x00006000 0x00006000 0x00060 0x00060 RW 0x4
GNU_RELRO 0x007000 0x00006000 0x00006000 0x0006c 0x01000 R 0x1
GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RW 0
EXIDX 0x006800 0x00005800 0x00005800 0x002b8 0x002b8 R 0x4

Nothing wrong with that from a strict ELF compliance point of view, but
it doesn't meet the requirements of our current gen_ldelf_hex.py script
which makes the build fail:

$ scripts/gen_ldelf_hex.py --input out/arm-plat-vexpress/ldelf/ldelf.elf \
--output out/arm-plat-vexpress/core/ldelf_hex.c
Expected load segment to be read/write

I think our script is a bit too strict, what really matters is that
OP-TEE creates two memory mappings for the PT_LOAD segments of ldelf,
one is RX and the other is RW. We can therefore concatenate segments as
long as we have one or more non-writable segments followed by one or
more writable ones.

This commit relaxes the requirements in gen_ldelf_hex.py and implements
the above conditions instead.

[1] clang version 11.0.0 (https://github.com/llvm/llvm-project.git
6b3168f8cdb46656330929877b0b4daab35d30de)

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU, GCC 8.3/Clang 10/Clang pre-11)
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMUv8, GCC 8.3/Clang 10)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>