Searched hist:c6ac89bc911f82c4a37b63cf005fb7723541c8a3 (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/include/drivers/ |
| H A D | imx_snvs.h | c6ac89bc911f82c4a37b63cf005fb7723541c8a3 Tue Jul 18 12:05:36 UTC 2017 Peng Fan <peng.fan@nxp.com> drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.
Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.
The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/drivers/ |
| H A D | imx_snvs.c | c6ac89bc911f82c4a37b63cf005fb7723541c8a3 Tue Jul 18 12:05:36 UTC 2017 Peng Fan <peng.fan@nxp.com> drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.
Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.
The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | sub.mk | c6ac89bc911f82c4a37b63cf005fb7723541c8a3 Tue Jul 18 12:05:36 UTC 2017 Peng Fan <peng.fan@nxp.com> drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.
Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.
The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/plat-imx/ |
| H A D | imx-regs.h | c6ac89bc911f82c4a37b63cf005fb7723541c8a3 Tue Jul 18 12:05:36 UTC 2017 Peng Fan <peng.fan@nxp.com> drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.
Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.
The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|