| /rk3399_ARM-atf/include/lib/extensions/ |
| H A D | mpam.h | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/lib/extensions/mpam/ |
| H A D | mpam.c | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/make_helpers/ |
| H A D | constraints.mk | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| H A D | arch_features.mk | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/common/ |
| H A D | feat_detect.c | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch_helpers.h | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| H A D | arch_features.h | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| H A D | arch.h | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | platform.mk | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|
| /rk3399_ARM-atf/ |
| H A D | Makefile | c42aefd3eb1b5888ee6f3d1f8645b62ec850cdcc Tue Aug 12 21:02:08 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support
Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.
When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.
At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e
|