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/rk3399_rockchip-uboot/board/freescale/ls2080aqds/
H A D	ddr.c	`c4243ac9e2713897a63dcdc3a96bf088fdb49866 Wed Nov 04 18:03:22 UTC 2015 York Sun <yorksun@freescale.com> armv8/ls2080aqds: Update DDR settings for four chip-select case When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>`