Searched hist:c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | smccc_macros.S | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Tue Aug 20 14:22:44 UTC 2019 Alexei Fedorov <Alexei.Fedorov@arm.com> AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| H A D | el3_common_macros.S | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Tue Aug 20 14:22:44 UTC 2019 Alexei Fedorov <Alexei.Fedorov@arm.com> AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| H A D | arch.h | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Tue Aug 20 14:22:44 UTC 2019 Alexei Fedorov <Alexei.Fedorov@arm.com> AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
| /rk3399_ARM-atf/bl32/sp_min/aarch32/ |
| H A D | entrypoint.S | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Tue Aug 20 14:22:44 UTC 2019 Alexei Fedorov <Alexei.Fedorov@arm.com> AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch32/ |
| H A D | context_mgmt.c | c3e8b0be9bde36d220beea5d0452ecd04dcd94c6 Tue Aug 20 14:22:44 UTC 2019 Alexei Fedorov <Alexei.Fedorov@arm.com> AArch32: Disable Secure Cycle Counter
This patch changes implementation for disabling Secure Cycle
Counter. For ARMv8.5 the counter gets disabled by setting
SDCR.SCCD bit on CPU cold/warm boot. For the earlier
architectures PMCR register is saved/restored on secure
world entry/exit from/to Non-secure state, and cycle counting
gets disabled by setting PMCR.DP bit.
In 'include\aarch32\arch.h' header file new
ARMv8.5-PMU related definitions were added.
Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
|