Searched hist:c1da286a086ecbd7b2ee6837047dcc5707cf985f (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/lib/ |
| H A D | setjmp.S | c1da286a086ecbd7b2ee6837047dcc5707cf985f Tue Oct 10 14:21:13 UTC 2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers. One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.
To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.
Change-Id: I9403d28218f03cdf84b1e8cbd4d3d4eef790e9b9
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
| H A D | setjmp_aarch64.S | c1da286a086ecbd7b2ee6837047dcc5707cf985f Tue Oct 10 14:21:13 UTC 2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers. One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.
To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.
Change-Id: I9403d28218f03cdf84b1e8cbd4d3d4eef790e9b9
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
| H A D | Makefile | c1da286a086ecbd7b2ee6837047dcc5707cf985f Tue Oct 10 14:21:13 UTC 2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers. One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.
To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.
Change-Id: I9403d28218f03cdf84b1e8cbd4d3d4eef790e9b9
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | setjmp.h | c1da286a086ecbd7b2ee6837047dcc5707cf985f Tue Oct 10 14:21:13 UTC 2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> UPSTREAM: arm: provide a PCS-compliant setjmp implementation
The previous setjmp-implementation (as a static inline function that
contained an 'asm volatile' sequence) was extremely fragile: (some
versions of) GCC optimised the set of registers. One critical example
was the removal of 'r9' from the clobber list, if -ffixed-reg9 was
supplied.
To increase robustness and ensure PCS-compliant behaviour, the setjmp
and longjmp implementation are now in assembly and closely match what
one would expect to find in a libc implementation.
Change-Id: I9403d28218f03cdf84b1e8cbd4d3d4eef790e9b9
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|