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/rk3399_rockchip-uboot/include/configs/
H A DMPC8536DS.hc0391111c33c22fabeddf8f4ca801ec7645b4f5c Sat Sep 27 06:40:57 UTC 2008 Jason Jin <Jason.jin@freescale.com> Fix the incorrect DDR clk freq reporting on 8536DS

On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>