Searched hist:bf3877e072af2b718454e9ee1ee16d769980378e (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_cache.S | bf3877e072af2b718454e9ee1ee16d769980378e Fri Nov 08 16:14:47 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): handle cold reset via physical reset switch
On the Agilex5 platform when cold reset is issued via CLI application
in the OS, it is received in the BL31 via a SMC call and handled
accordingly like flush/invalidate the caches. However, when the cold
reset is issued via an external switch these handlings are missed.
This patch addresses those missed cache operations.
Also, this patch is to restoring SCR_EL3 NS bit to its previous value
in order to avoid unintended behavior especially if subsequent code
expects the SCR_EL3 register to be in its original configuration.
Change-Id: I9737f2db649e483ba61fffa6eeb0b56a9d15074a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/ |
| H A D | bl31_plat_setup.c | bf3877e072af2b718454e9ee1ee16d769980378e Fri Nov 08 16:14:47 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): handle cold reset via physical reset switch
On the Agilex5 platform when cold reset is issued via CLI application
in the OS, it is received in the BL31 via a SMC call and handled
accordingly like flush/invalidate the caches. However, when the cold
reset is issued via an external switch these handlings are missed.
This patch addresses those missed cache operations.
Also, this patch is to restoring SCR_EL3 NS bit to its previous value
in order to avoid unintended behavior especially if subsequent code
expects the SCR_EL3 register to be in its original configuration.
Change-Id: I9737f2db649e483ba61fffa6eeb0b56a9d15074a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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