Searched hist:b93bed43fef08aff6ad0b9fbf7310e8a822579d0 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/ |
| H A D | usbplug.c | b93bed43fef08aff6ad0b9fbf7310e8a822579d0 Mon Jan 29 10:20:01 UTC 2024 Yifeng Zhao <yifeng.zhao@rock-chips.com> rockchip: rk3576: Update arch_cpu_init()
- Enable usb otg0 to debug in spl
This patch enable usb otg0 to uart/jtag for debug.
By default, otg0 is in usb mode, and auto switch
dp/dm to uart mode or jtag mode by hardware if
successfully handshake with SE0/SE1 and K/J state
sequence.
- fix the default val of SYS_GRF_SOC_CON2[12]
- Set combophy0/1 and usb2 phy1 to save power
Assert reset the combophy0/1 for lowest power consumption.
Assert siddq for usb2 phy1 to power down analog block.
- Fix usbplug fspi iomux
- add mcu support
- Add GPIO0B0~B3 PULL and IE
- set usb3 otg0 pipe phy status
This patch sets the usb3 otg0 pipe phy status to 0
instead of from usb3 phy to ensure that rockusb can
work at high-speed even if usb3 phy isn't ready.
- Add iomux for usbplug
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I41db73f4d4f86421c8b911e8190aec4b44d14ec5
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3576/ |
| H A D | rk3576.c | b93bed43fef08aff6ad0b9fbf7310e8a822579d0 Mon Jan 29 10:20:01 UTC 2024 Yifeng Zhao <yifeng.zhao@rock-chips.com> rockchip: rk3576: Update arch_cpu_init()
- Enable usb otg0 to debug in spl
This patch enable usb otg0 to uart/jtag for debug.
By default, otg0 is in usb mode, and auto switch
dp/dm to uart mode or jtag mode by hardware if
successfully handshake with SE0/SE1 and K/J state
sequence.
- fix the default val of SYS_GRF_SOC_CON2[12]
- Set combophy0/1 and usb2 phy1 to save power
Assert reset the combophy0/1 for lowest power consumption.
Assert siddq for usb2 phy1 to power down analog block.
- Fix usbplug fspi iomux
- add mcu support
- Add GPIO0B0~B3 PULL and IE
- set usb3 otg0 pipe phy status
This patch sets the usb3 otg0 pipe phy status to 0
instead of from usb3 phy to ensure that rockusb can
work at high-speed even if usb3 phy isn't ready.
- Add iomux for usbplug
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I41db73f4d4f86421c8b911e8190aec4b44d14ec5
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