Searched hist:b5c8753fa173d6372d86dcd11f83ef23c911b0de (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | speed.c | b5c8753fa173d6372d86dcd11f83ef23c911b0de Wed Feb 16 08:03:29 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Fixup determining PME, FMan freq
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.
We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)
On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL. On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.
On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | config_mpc85xx.h | b5c8753fa173d6372d86dcd11f83ef23c911b0de Wed Feb 16 08:03:29 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Fixup determining PME, FMan freq
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.
We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)
On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL. On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.
On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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