Searched hist:ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/armv8/ |
| H A D | mmu.h | ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 Thu Aug 20 09:52:14 UTC 2015 Thierry Reding <treding@nvidia.com> armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/ |
| H A D | cache_v8.c | ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 Thu Aug 20 09:52:14 UTC 2015 Thierry Reding <treding@nvidia.com> armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|