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| H A D | gicv2_helpers.c | a91e12fbeac527df82b39d763a68f00d1d890cdc Fri Jan 15 14:05:37 UTC 2016 Soby Mathew <soby.mathew@arm.com> Fix race in GIC IPRIORITY and ITARGET accessors
GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a single byte write. The previous implementation of
gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
accesses, modifying values for 4 interrupts at a time, using a
read-modify-write approach. This potentially may cause concurrent changes
by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
the issue by modifying these accessors to use byte addressing.
Fixes ARM-software/tf-issues#343
Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915
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