Searched hist:a86abe43ddf2c06b5d3162373e927ff90ba25f62 (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32-core.c | a86abe43ddf2c06b5d3162373e927ff90ba25f62 Wed Aug 28 14:10:33 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> clk: stm32mp1: add dsb in clock driver
Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before disabling the clocks and return to caller only when
clock is enabled, so before any accesses to the clocked devices.
As the registers are mapped as device memory (shareable, bufferable),
the order of operation is guaranteed only at outer shareable limit
and not on each device, for example when they are not on the same bus.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| H A D | clk-stm32mp15.c | a86abe43ddf2c06b5d3162373e927ff90ba25f62 Wed Aug 28 14:10:33 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> clk: stm32mp1: add dsb in clock driver
Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before disabling the clocks and return to caller only when
clock is enabled, so before any accesses to the clocked devices.
As the registers are mapped as device memory (shareable, bufferable),
the order of operation is guaranteed only at outer shareable limit
and not on each device, for example when they are not on the same bus.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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