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| H A D | freeze_controller.c | a8535c306c68eb050ad0835845ea87a856b192f1 Mon Aug 10 22:49:09 UTC 2015 Marek Vasut <marex@denx.de> arm: socfpga: Fix delay in freeze controller
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.
Signed-off-by: Marek Vasut <marex@denx.de>
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